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Searched refs:HalfWordAccess (Results 1 – 6 of 6) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonBaseInfo.h77 HalfWordAccess = 2, // Half word access instruction (memh). enumerator
HDHexagonMCCodeEmitter.cpp327 case HexagonII::MemAccessSize::HalfWordAccess: in getFixupNoBits()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrInfo.td1719 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1730 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1765 let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in
1914 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1929 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1970 let accessSize = HalfWordAccess, opExtentAlign = 1 in
2002 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
2003 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
2006 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2059 let accessSize = HalfWordAccess in {
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HDHexagonInstrInfoV4.td421 let accessSize = HalfWordAccess, hasNewValue = 1 in {
442 let accessSize = HalfWordAccess in
479 let accessSize = HalfWordAccess in {
620 let hasNewValue = 1, accessSize = HalfWordAccess in {
712 HalfWordAccess>;
717 0b011, HalfWordAccess, 1>;
748 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
783 HalfWordAccess>;
785 HalfWordAccess, 1>;
841 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
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HDHexagonIsetDx.td106 let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
233 let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in
303 let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
HDHexagonInstrFormats.td57 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).