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Searched refs:InstrItins (Results 1 – 24 of 24) sorted by relevance

/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetSchedule.cpp35 return EnableSchedItins && !InstrItins.isEmpty(); in hasInstrItineraries()
59 STI->initInstrItins(InstrItins); in init()
79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
80 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI); in getNumMicroOps()
164 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, in computeOperandLatency()
169 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx); in computeOperandLatency()
175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); in computeOperandLatency()
259 return TII->getInstrLatency(&InstrItins, MI); in computeInstrLatency()
HDDFAPacketizer.cpp36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT), in DFAPacketizer()
68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); in canReserveResources()
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); in reserveResources()
HDPostRASchedulerList.cpp201 const InstrItineraryData *InstrItins = in SchedulePostRATDList() local
205 InstrItins, this); in SchedulePostRATDList()
HDTwoAddressInstructionPass.cpp76 const InstrItineraryData *InstrItins; member in __anon0a2cc79c0111::TwoAddressInstructionPass
867 if (TII->getInstrLatency(InstrItins, MI) > 1) in rescheduleMIBelowKill()
1001 if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist)) in isDefTooClose()
1599 InstrItins = MF->getSubtarget().getInstrItineraryData(); in runOnMachineFunction()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonSubtarget.h52 InstrItineraryData InstrItins; variable
61 return &InstrItins; in getInstrItineraryData()
HDHexagonSubtarget.cpp80 InstrItins = getInstrItineraryForCPU(CPUString); in HexagonSubtarget()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDTargetSchedule.h36 InstrItineraryData InstrItins; variable
80 return &InstrItins; in getInstrItineraries()
HDDFAPacketizer.h46 const InstrItineraryData *InstrItins; variable
82 const InstrItineraryData *getInstrItins() const { return InstrItins; } in getInstrItins()
HDResourcePriorityQueue.h63 const InstrItineraryData* InstrItins; variable
/NextBSD/contrib/llvm/lib/MC/
HDMCSubtargetInfo.cpp109 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { in initInstrItins()
110 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUSubtarget.h97 InstrItineraryData InstrItins; variable
119 return &InstrItins; in getInstrItineraryData()
HDAMDGPUSubtarget.cpp80 InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) { in AMDGPUSubtarget()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSubtarget.h133 InstrItineraryData InstrItins; variable
292 return &InstrItins; in getInstrItineraryData()
HDMipsSubtarget.cpp149 InstrItins = getInstrItineraryForCPU(CPUName); in initializeSubtargetDependencies()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCSubtarget.h76 InstrItineraryData InstrItins; variable
157 return &InstrItins; in getInstrItineraryData()
HDPPCSubtarget.cpp117 InstrItins = getInstrItineraryForCPU(CPUName); in initSubtargetFeatures()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMSubtarget.h232 InstrItineraryData InstrItins; variable
445 return &InstrItins; in getInstrItineraryData()
HDARMSubtarget.cpp207 InstrItins = getInstrItineraryForCPU(CPUString); in initSubtargetFeatures()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86Subtarget.h229 InstrItineraryData InstrItins; variable
503 return &InstrItins; in getInstrItineraryData()
HDX86Subtarget.cpp198 InstrItins = getInstrItineraryForCPU(CPUName); in initSubtargetFeatures()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDScheduleDAGSDNodes.cpp50 InstrItins(mf.getSubtarget().getInstrItineraryData()) {} in ScheduleDAGSDNodes()
608 if (!InstrItins || InstrItins->isEmpty()) { in computeLatency()
622 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
HDScheduleDAGSDNodes.h40 const InstrItineraryData *InstrItins; variable
HDResourcePriorityQueue.cpp45 : Picker(this), InstrItins(IS->MF->getSubtarget().getInstrItineraryData()) { in ResourcePriorityQueue()
320 if (Packet.size() >= InstrItins->SchedModel.IssueWidth) { in reserveResources()
/NextBSD/contrib/llvm/include/llvm/MC/
HDMCSubtargetInfo.h158 void initInstrItins(InstrItineraryData &InstrItins) const;