Home
last modified time | relevance | path

Searched refs:LS (Results 1 – 25 of 101) sorted by relevance

12345

/NextBSD/contrib/llvm/lib/Transforms/Scalar/
HDInductiveRangeCheckElimination.cpp563 changeIterationSpaceEnd(const LoopStructure &LS, BasicBlock *Preheader,
570 BasicBlock *createPreheader(const LoopStructure &LS, BasicBlock *OldPreheader,
578 LoopStructure &LS, BasicBlock *ContinuationBlockAndPreheader,
610 LoopConstrainer(Loop &L, LoopInfo &LI, const LoopStructure &LS, in LoopConstrainer() argument
615 MainLoopStructure(LS) {} in LoopConstrainer()
968 const LoopStructure &LS, BasicBlock *Preheader, Value *ExitSubloopAt, in changeIterationSpaceEnd() argument
1045 auto BBInsertLocation = std::next(Function::iterator(LS.Latch)); in changeIterationSpaceEnd()
1046 RRI.ExitSelector = BasicBlock::Create(Ctx, Twine(LS.Tag) + ".exit.selector", in changeIterationSpaceEnd()
1048 RRI.PseudoExit = BasicBlock::Create(Ctx, Twine(LS.Tag) + ".pseudo.exit", &F, in changeIterationSpaceEnd()
1052 bool Increasing = LS.IndVarIncreasing; in changeIterationSpaceEnd()
[all …]
/NextBSD/contrib/llvm/lib/CodeGen/
HDStackSlotColoring.cpp49 LiveStacks* LS; member in __anon034821580111::StackSlotColoring
156 if (!LS->hasInterval(FI)) in ScanForSpillSlotRefs()
158 LiveInterval &li = LS->getInterval(FI); in ScanForSpillSlotRefs()
189 Intervals.reserve(LS->getNumIntervals()); in InitializeSlots()
190 for (auto &I : *LS) in InitializeSlots()
434 LS = &getAnalysis<LiveStacks>(); in runOnMachineFunction()
439 unsigned NumSlots = LS->getNumIntervals(); in runOnMachineFunction()
HDLiveDebugVariables.cpp83 LexicalScopes &LS; member in __anonc6fb9c530111::UserValueScopes
87 UserValueScopes(DebugLoc D, LexicalScopes &L) : DL(D), LS(L) {} in UserValueScopes()
93 LS.getMachineBasicBlocks(DL, LBlocks); in dominates()
94 if (LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB)) in dominates()
285 LexicalScopes LS; member in __anonc6fb9c530311::LDVImpl
344 LS.reset(); in clear()
728 UserValueScopes UVS(userValues[i]->getDebugLoc(), LS); in computeIntervals()
740 LS.initialize(mf); in runOnMachineFunction()
/NextBSD/contrib/llvm/lib/Analysis/
HDCostModel.cpp178 ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(L); in matchPairwiseReductionAtLevel() local
179 if (!LS && Level) in matchPairwiseReductionAtLevel()
186 if (!Level && !RS && !LS) in matchPairwiseReductionAtLevel()
190 Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr; in matchPairwiseReductionAtLevel()
226 if (matchPairwiseShuffleMask(LS, true, Level)) { in matchPairwiseReductionAtLevel()
230 if (!matchPairwiseShuffleMask(LS, false, Level)) in matchPairwiseReductionAtLevel()
/NextBSD/contrib/llvm/lib/Target/ARM/MCTargetDesc/
HDARMBaseInfo.h39 LS, // Unsigned lower or same Less than or equal enumerator
58 case HI: return LS; in getOppositeCondition()
59 case LS: return HI; in getOppositeCondition()
79 case ARMCC::LS: return "ls"; in ARMCondCodeToString()
/NextBSD/sys/cam/scsi/
HDscsi_ses.h40 #define GEN_GETTER(LS, US, LF, UF) \ argument
42 LS ## _get_ ## LF(struct LS *elem) { \
47 #define GEN_SETTER(LS, US, LF, UF) \ argument
49 LS ## _set_ ## LF(struct LS *elem, int val) { \
55 #define GEN_HDR_GETTER(LS, US, LF, UF) \ argument
57 LS ## _get_ ## LF(struct LS *page) { \
62 #define GEN_HDR_SETTER(LS, US, LF, UF) \ argument
64 LS ## _set_ ## LF(struct LS *page, int val) { \
70 #define GEN_ACCESSORS(LS, US, LF, UF) \ argument
71 GEN_GETTER(LS, US, LF, UF) \
[all …]
/NextBSD/contrib/binutils/include/opcode/
HDspu-insns.h141 APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */
142 APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */
152 APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */
153 APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16…
158 APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */
159 APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */
162 APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10…
168 APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */
187 APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<…
196 APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */
[all …]
/NextBSD/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/
HDPthreadLockChecker.cpp221 LockSetTy LS = state->get<LockSet>(); in ReleaseLock() local
225 if (!LS.isEmpty()) { in ReleaseLock()
226 const MemRegion *firstLockR = LS.getHead(); in ReleaseLock()
241 state = state->set<LockSet>(LS.getTail()); in ReleaseLock()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMips16ISelDAGToDAG.cpp229 const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent); in selectAddr16() local
231 if (LS) { in selectAddr16()
232 if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2()) in selectAddr16()
234 if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2()) in selectAddr16()
/NextBSD/contrib/llvm/lib/CodeGen/AsmPrinter/
HDDwarfFile.cpp138 bool DwarfFile::addScopeVariable(LexicalScope *LS, DbgVariable *Var) { in addScopeVariable() argument
139 SmallVectorImpl<DbgVariable *> &Vars = ScopeVariables[LS]; in addScopeVariable()
HDDwarfFile.h100 bool addScopeVariable(LexicalScope *LS, DbgVariable *Var);
/NextBSD/contrib/groff/contrib/mom/examples/
HDtypesetting.mom20 .LS 14 \" Leading (line spacing)
41 .LS 11 \" New leading
135 .LS -.5 \" Reduce leading by 1/2 point
177 .LS 14
193 .LS 14
288 .LS 14
298 .LS 13
376 .LS 14
387 .LS 13
486 .LS 14
[all …]
/NextBSD/contrib/gcc/config/mips/
HDsb1.md113 ;; an EX unit. Can not co-issue if the dependent insn executes on an LS unit.
210 ;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX
212 ;; another LS insn (excluding store data). A simple alu insn issued on an EX
213 ;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding
225 ;; ??? Optimal scheduling taking the LS units into account seems to require
228 ;; LS unit. Also, we need to prune the list to ensure we don't overschedule
229 ;; insns to the LS unit, and that we don't conflict with insns that need LS1
266 ;; result goes to a LS unit (excluding store data).
330 ;; mul latency is 7 cycles if the result is used by any LS insn.
/NextBSD/sys/gnu/dts/arm/
HDkirkwood-lschlv2.dts6 model = "Buffalo Linkstation LS-CHLv2";
HDkirkwood-lsxhl.dts6 model = "Buffalo Linkstation LS-XHL";
/NextBSD/contrib/groff/contrib/mom/
HDBUGS72 When LS is invoked after a single text line at the top of a page
77 Changes made to ALD and LS in version 1.2-c should not apply when
90 First .LS call after a top margin has been set (with .T_MARGIN
92 there are conflicts between ALD, LS and T_MARGIN.
HDChangeLog94 o Reworked handling of ALD/SPACE/SP and LS when they're used at
97 more intuitive: ALD after LS advances the specified distance from
98 the top baseline; LS after ALD doesn't change the position of the
141 o Added an .if \\n(.n=0 if to the ie clause in LS that controls how mom
142 responds to initial LS invocation at page top if T_MARGIN has
143 been set. Now, if there's text on the "top" baseline, LS behaves
701 - added some "resets" (LL, LS, QUAD)
780 o Fixed T_MARGIN, LS, and AUTOLEAD so that if T_MARGIN is set before LS
782 properly on the baseline set by T_MARGIN. Previously, LS and
797 has the choice. Incorporated appropriate changes to PS and LS.
[all …]
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTX.h168 LS, enumerator
/NextBSD/etc/
HDdisktab76 # LS-120 floppy-format.
78 fd120m|floppy120|floppy120m|3.5in LS-120 Floppy:\
/NextBSD/share/syscons/fonts/
HDiso08-8x8.fnt23 M9GQ@\```=LS,?`P>``#<=F9@\````#Y@/`9\`!`P?#`P-!@```#,S,S,=@``
HDiso07-8x8.fnt23 M9GQ@\```=LS,?`P>``#<=F!@\````'[`?`;\`#`P_#`P-AP```#,S,S,=@``
HDiso04-vga9-8x8.fnt23 M9GQ@\```=LS,?`X.````W&9@8/````!\P'P&_``P,/PP,#8<````S,S,S'8`
HDiso02-8x8.fnt23 M9GQ@\```=LS,?`P>``#<=F9@\````#Y@/`9\`!`P?#`P-!@```#,S,S,=@``
HDiso04-8x8.fnt23 M9GQ@\```=LS,?`X.````W&9@8/````!\P'P&_``P,/PP,#8<````S,S,S'8`
/NextBSD/contrib/llvm/lib/Target/AArch64/Utils/
HDAArch64BaseInfo.h203 LS = 0x9, // Unsigned lower or same Less than or equal enumerator
226 case LS: return "ls"; in getCondCodeName()
260 case LS: return 0; // C == 0 || Z == 1 in getNZCVToSatisfyCondCode()

12345