Searched refs:LSR (Results 1 – 10 of 10) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| HD | AArch64AddressingModes.h | 35 LSR, enumerator
56 case AArch64_AM::LSR: return "lsr"; in getShiftExtendName()
77 case 1: return AArch64_AM::LSR; in getShiftType()
105 case AArch64_AM::LSR: STEnc = 1; break; in getShifterImm()
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| /NextBSD/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/ |
| HD | ARMUtils.h | 130 static inline uint32_t LSR(const uint32_t value, const uint32_t amount, bool *success) in LSR() function
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| /NextBSD/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| HD | AArch64AsmParser.cpp | 959 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1017 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1028 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isLogicalShifter()
2308 .Case("lsr", AArch64_AM::LSR) in tryParseOptionalShiftExtend()
2330 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/Utils/ |
| HD | AArch64BaseInfo.h | 481 LSR, enumerator
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMInstrThumb.td | 1016 // LSR immediate
1027 // LSR register
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| HD | ARMInstrInfo.td | 5649 // LSR, ROR, and RRX instructions.
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelDAGToDAG.cpp | 306 return AArch64_AM::LSR; in getShiftTypeForNode()
1723 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) { in getUsefulBitsFromOrWithShiftedReg()
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| HD | AArch64FastISel.cpp | 1208 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break; in emitAddSub()
3639 /*IsKill=*/false, AArch64_AM::LSR, 32, in fastLowerIntrinsicCall()
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| /NextBSD/secure/lib/libcrypto/amd64/ |
| HD | bsaes-x86_64.S | 2460 .LSR: label
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| /NextBSD/contrib/binutils/gas/ |
| HD | ChangeLog-0001 | 5275 Issue a warning if "ASR #0" or "LSR #0" is used.
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