Home
last modified time | relevance | path

Searched refs:MRI (Results 1 – 25 of 277) sorted by relevance

12345678910>>...12

/NextBSD/contrib/binutils/ld/
HDldlex.l117 %s MRI
147 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
153 <MRI,EXPRESSION>([0-9A-Fa-f])+(H|h|X|x|B|b|O|o|D|d) {
178 <SCRIPT,DEFSYMEXP,MRI,BOTH,EXPRESSION>((("$"|0[xX])([0-9A-Fa-f])+)|(([0-9])+))(M|K|m|k)? {
207 <BOTH,SCRIPT,EXPRESSION,MRI>"]" { RTOKEN(']');}
208 <BOTH,SCRIPT,EXPRESSION,MRI>"[" { RTOKEN('[');}
209 <BOTH,SCRIPT,EXPRESSION,MRI>"<<=" { RTOKEN(LSHIFTEQ);}
210 <BOTH,SCRIPT,EXPRESSION,MRI>">>=" { RTOKEN(RSHIFTEQ);}
211 <BOTH,SCRIPT,EXPRESSION,MRI>"||" { RTOKEN(OROR);}
212 <BOTH,SCRIPT,EXPRESSION,MRI>"==" { RTOKEN(EQ);}
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in __anonb0a0f54b0111::AArch64AdvSIMDScalar
102 const MachineRegisterInfo *MRI) { in isGPR64() argument
106 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
111 const MachineRegisterInfo *MRI) { in isFPR64() argument
113 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
115 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
125 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
142 MRI) && in getSrcFromCopy()
143 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
146 MRI) && in getSrcFromCopy()
[all …]
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCVSXCopy.cpp58 MachineRegisterInfo &MRI) { in IsRegInClass()
60 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
68 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
69 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
72 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
73 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
76 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
77 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
84 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in processBlock() local
94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
[all …]
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIFixSGPRCopies.cpp89 const MachineRegisterInfo &MRI,
93 const MachineRegisterInfo &MRI,
97 const MachineRegisterInfo &MRI) const;
119 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVGPROperands() local
125 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
136 const MachineRegisterInfo &MRI, in inferRegClassFromUses() argument
142 MRI.getRegClass(Reg) : in inferRegClassFromUses()
147 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) { in inferRegClassFromUses()
150 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, in inferRegClassFromUses()
162 const MachineRegisterInfo &MRI, in inferRegClassFromDef() argument
[all …]
HDSIShrinkInstructions.cpp76 const MachineRegisterInfo &MRI) { in isVGPR() argument
81 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg())); in isVGPR()
88 const MachineRegisterInfo &MRI) { in canShrink() argument
102 if (!isVGPR(Src2, TRI, MRI) || in canShrink()
116 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) in canShrink()
139 MachineRegisterInfo &MRI, bool TryToCommute = true) { in foldImmediates() argument
141 if (!MRI.isSSA()) in foldImmediates()
160 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) in foldImmediates()
164 if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) { in foldImmediates()
166 MachineInstr *Def = MRI.getUniqueVRegDef(Reg); in foldImmediates()
[all …]
HDSIInstrInfo.cpp921 unsigned Reg, MachineRegisterInfo *MRI) const { in FoldImmediate()
922 if (!MRI->hasOneNonDBGUse(Reg)) in FoldImmediate()
943 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
947 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) in FoldImmediate()
995 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); in FoldImmediate()
1007 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) in FoldImmediate()
1011 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
1037 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); in FoldImmediate()
1290 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI, in usesConstantBus() argument
1301 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); in usesConstantBus()
[all …]
HDR600OptimizeVectorRegisters.cpp50 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { in isImplicitlyDef() argument
51 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), in isImplicitlyDef()
52 E = MRI.def_instr_end(); It != E; ++It) { in isImplicitlyDef()
55 if (MRI.isReserved(Reg)) { in isImplicitlyDef()
67 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo() argument
72 if (isImplicitlyDef(MRI, MO.getReg())) in RegSeqInfo()
87 MachineRegisterInfo *MRI; member in __anon0d8035e60111::R600VectorRegMerger
191 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); in RebuildVector()
218 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), in RebuildVector()
219 E = MRI->use_instr_end(); It != E; ++It) { in RebuildVector()
[all …]
HDSILowerI1Copies.cpp73 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
90 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in runOnMachineFunction()
92 MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass); in runOnMachineFunction()
106 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction()
107 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction()
114 MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg()); in runOnMachineFunction()
148 MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass); in runOnMachineFunction()
/NextBSD/contrib/llvm/lib/CodeGen/
HDRegAllocBase.cpp61 MRI = &vrm.getRegInfo(); in init()
65 MRI->freezeReservedRegs(vrm.getMachineFunction()); in init()
74 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in seedLiveRegs()
76 if (MRI->reg_nodbg_empty(Reg)) in seedLiveRegs()
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
117 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
131 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
142 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) { in allocatePhysRegs()
HDPeepholeOptimizer.cpp113 MachineRegisterInfo *MRI; member in __anonc2f739380111::PeepholeOptimizer
209 const MachineRegisterInfo &MRI; member in __anonc2f739380111::ValueTracker
248 const MachineRegisterInfo &MRI, in ValueTracker() argument
252 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
254 Def = MRI.getVRegDef(Reg); in ValueTracker()
255 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
267 const MachineRegisterInfo &MRI, in ValueTracker() argument
271 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
326 if (MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
332 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
[all …]
HDVirtRegMap.cpp57 MRI = &mf.getRegInfo(); in runOnMachineFunction()
85 unsigned Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference()
122 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in print()
127 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
131 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in print()
135 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
162 MachineRegisterInfo *MRI; member in __anonbbb9c0a40111::VirtRegRewriter
212 MRI = &MF->getRegInfo(); in runOnMachineFunction()
236 MRI->clearVirtRegs(); in runOnMachineFunction()
[all …]
HDLLVMTargetMachine.cpp46 MRI = TheTarget.createMCRegInfo(getTargetTriple().str()); in initAsmInfo()
56 TheTarget.createMCAsmInfo(*MRI, getTargetTriple().str()); in initAsmInfo()
165 const MCRegisterInfo &MRI = *getMCRegisterInfo(); in addPassesToEmitFile() local
173 getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI); in addPassesToEmitFile()
178 MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); in addPassesToEmitFile()
181 getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); in addPassesToEmitFile()
193 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); in addPassesToEmitFile()
195 getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); in addPassesToEmitFile()
245 const MCRegisterInfo &MRI = *getMCRegisterInfo(); in addPassesToEmitMC() local
247 getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx); in addPassesToEmitMC()
[all …]
HDOptimizePHIs.cpp33 MachineRegisterInfo *MRI; member in __anonc0285dc80111::OptimizePHIs
69 MRI = &Fn.getRegInfo(); in runOnMachineFunction()
107 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
114 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); in IsSingleValuePHICycle()
147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) { in IsDeadPHICycle()
171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
174 MRI->replaceRegWith(OldReg, SingleValReg); in OptimizeBB()
HDMachineCSE.cpp48 MachineRegisterInfo *MRI; member in __anon843b19730111::MachineCSE
132 bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg); in INITIALIZE_PASS_DEPENDENCY()
133 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY()
155 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY()
156 if (!MRI->constrainRegClass(SrcReg, RC)) in INITIALIZE_PASS_DEPENDENCY()
162 MRI->clearKillFlags(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
233 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent())) in hasLivePhysRegDefUses()
285 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i])) in PhysRegDefsReach()
376 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) { in isProfitableToCSE()
379 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { in isProfitableToCSE()
[all …]
HDMachineSink.cpp59 MachineRegisterInfo *MRI; // Machine register information member in __anond112e00d0111::MachineSinking
166 !MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
169 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
170 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
174 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
179 MRI->replaceRegWith(DstReg, SrcReg); in INITIALIZE_PASS_DEPENDENCY()
184 MRI->clearKillFlags(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
204 if (MRI->use_nodbg_empty(Reg)) in AllUsesDominatedByBlock()
223 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in AllUsesDominatedByBlock()
236 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in AllUsesDominatedByBlock()
[all …]
/NextBSD/contrib/llvm/lib/Target/ARM/
HDA15SDOptimizer.cpp62 MachineRegisterInfo *MRI; member
145 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
163 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
230 II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end(); in eraseInstrWithNoUses()
262 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern()
263 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern()
282 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
283 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
314 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
357 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopies()
[all …]
HDMLxExpansionPass.cpp53 MachineRegisterInfo *MRI; member
95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
120 !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
131 !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
149 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
160 DefMI = MRI->getVRegDef(SrcReg); in hasLoopHazard()
[all …]
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcFrameLowering.cpp111 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); in emitPrologue() local
112 unsigned regFP = MRI->getDwarfRegNum(SP::I6, true); in emitPrologue()
125 unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true); in emitPrologue()
126 unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true); in emitPrologue()
189 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) in verifyLeafProcRegUse() argument
193 if (MRI->isPhysRegUsed(reg)) in verifyLeafProcRegUse()
197 if (MRI->isPhysRegUsed(reg)) in verifyLeafProcRegUse()
206 MachineRegisterInfo &MRI = MF.getRegInfo(); in isLeafProc() local
210 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed in isLeafProc()
211 || MRI.isPhysRegUsed(SP::O6) // %SP is used in isLeafProc()
[all …]
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXPeephole.cpp83 const auto &MRI = MF.getRegInfo(); in isCVTAToLocalCombinationCandidate() local
86 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg()); in isCVTAToLocalCombinationCandidate()
108 const auto &MRI = MF.getRegInfo(); in CombineCVTAToLocal() local
110 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg()); in CombineCVTAToLocal()
121 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) { in CombineCVTAToLocal()
144 const auto &MRI = MF.getRegInfo(); in runOnMachineFunction() local
145 if (MRI.use_empty(NVPTX::VRFrame)) { in runOnMachineFunction()
146 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) { in runOnMachineFunction()
/NextBSD/contrib/llvm/lib/Target/Mips/MCTargetDesc/
HDMipsMCTargetDesc.h39 const MCRegisterInfo &MRI,
42 const MCRegisterInfo &MRI,
46 const MCRegisterInfo &MRI,
49 const MCRegisterInfo &MRI,
52 const MCRegisterInfo &MRI,
55 const MCRegisterInfo &MRI,
/NextBSD/contrib/llvm/lib/Target/ARM/MCTargetDesc/
HDARMMCTargetDesc.h60 const MCRegisterInfo &MRI,
64 const MCRegisterInfo &MRI,
67 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
71 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
78 const MCRegisterInfo &MRI,
82 const MCRegisterInfo &MRI,
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonGenPredicate.cpp66 HexagonGenPredicate() : MachineFunctionPass(ID), TII(0), TRI(0), MRI(0) { in HexagonGenPredicate()
86 MachineRegisterInfo *MRI; member in __anon4b234de30111::HexagonGenPredicate
115 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
210 use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); in processPredicateGPR()
213 MachineInstr *DefI = MRI->getVRegDef(Reg.R); in processPredicateGPR()
236 MachineInstr *DefI = MRI->getVRegDef(Reg.R); in getPredRegFor()
250 unsigned NewPR = MRI->createVirtualRegister(PredRC); in getPredRegFor()
311 const MachineInstr *DefI = MRI->getVRegDef(PR.R); in isScalarPred()
318 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
404 Register NewPR = MRI->createVirtualRegister(PredRC); in convertToPredForm()
[all …]
HDHexagonHardwareLoops.cpp74 MachineRegisterInfo *MRI; member
353 MRI = &MF.getRegInfo(); in runOnMachineFunction()
417 MachineInstr *DI = MRI->getVRegDef(PhiOpReg); in findInductionRegister()
427 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) { in findInductionRegister()
445 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
481 IVOp = MRI->getVRegDef(F->first); in findInductionRegister()
570 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); in getLoopTripCount()
616 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()
664 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount()
667 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount()
[all …]
/NextBSD/contrib/llvm/lib/Target/BPF/MCTargetDesc/
HDBPFMCCodeEmitter.cpp32 const MCRegisterInfo &MRI; member in __anond339671e0111::BPFMCCodeEmitter
37 : MRI(mri), IsLittleEndian(IsLittleEndian) {} in BPFMCCodeEmitter()
64 const MCRegisterInfo &MRI, in createBPFMCCodeEmitter() argument
66 return new BPFMCCodeEmitter(MRI, true); in createBPFMCCodeEmitter()
70 const MCRegisterInfo &MRI, in createBPFbeMCCodeEmitter() argument
72 return new BPFMCCodeEmitter(MRI, false); in createBPFbeMCCodeEmitter()
80 return MRI.getEncodingValue(MO.getReg()); in getMachineOpValue()
159 Encoding = MRI.getEncodingValue(Op1.getReg()); in getMemoryOpValue()
/NextBSD/contrib/llvm/lib/Target/X86/MCTargetDesc/
HDX86MCTargetDesc.cpp69 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { in InitLLVM2SEHRegisterMapping() argument
72 unsigned SEH = MRI->getEncodingValue(Reg); in InitLLVM2SEHRegisterMapping()
73 MRI->mapLLVMRegToSEHReg(Reg, SEH); in InitLLVM2SEHRegisterMapping()
112 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, in createX86MCAsmInfo() argument
142 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); in createX86MCAsmInfo()
148 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); in createX86MCAsmInfo()
207 const MCRegisterInfo &MRI) { in createX86MCInstPrinter() argument
209 return new X86ATTInstPrinter(MAI, MII, MRI); in createX86MCInstPrinter()
211 return new X86IntelInstPrinter(MAI, MII, MRI); in createX86MCInstPrinter()

12345678910>>...12