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Searched refs:MachineInstrBuilder (Results 1 – 25 of 80) sorted by relevance

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/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineInstrBuilder.h45 class MachineInstrBuilder {
49 MachineInstrBuilder() : MF(nullptr), MI(nullptr) {} in MachineInstrBuilder() function
53 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {} in MachineInstrBuilder() function
68 MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
87 const MachineInstrBuilder &addImm(int64_t Val) const { in addImm()
92 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const { in addCImm()
97 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const { in addFPImm()
102 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
108 const MachineInstrBuilder &addFrameIndex(int Idx) const { in addFrameIndex()
113 const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx,
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrBuilder.h90 static inline const MachineInstrBuilder &
91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem()
98 static inline const MachineInstrBuilder &
99 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset()
107 static inline const MachineInstrBuilder &
108 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset()
115 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg()
122 static inline const MachineInstrBuilder &
123 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress()
148 static inline const MachineInstrBuilder &
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HDX86FrameLowering.h21 class MachineInstrBuilder; variable
150 MachineInstrBuilder BuildStackAdjustment(MachineBasicBlock &MBB,
HDX86ExpandPseudo.cpp98 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI()
111 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ExpandPseudoInsts.cpp50 static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI, in transferImpOps()
51 MachineInstrBuilder &DefMI) { in transferImpOps()
98 MachineInstrBuilder MIB = in tryOrrMovk()
108 MachineInstrBuilder MIB1 = in tryOrrMovk()
165 MachineInstrBuilder MIB = in tryToreplicateChunks()
185 MachineInstrBuilder MIB1 = in tryToreplicateChunks()
210 MachineInstrBuilder MIB2 = in tryToreplicateChunks()
348 MachineInstrBuilder MIB = in trySequenceOfOnes()
359 MachineInstrBuilder MIB1 = in trySequenceOfOnes()
376 MachineInstrBuilder MIB2 = in trySequenceOfOnes()
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HDAArch64LoadStoreOptimizer.cpp377 MachineInstrBuilder MIB = BuildMI(*I->getParent(), InsertionPoint, in mergePairedInsns()
413 MachineInstrBuilder MIBKill = in mergePairedInsns()
420 MachineInstrBuilder MIBSXTW = in mergePairedInsns()
688 MachineInstrBuilder MIB = in mergePreIdxUpdateInsn()
731 MachineInstrBuilder MIB = in mergePostIdxUpdateInsn()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMBaseInstrInfo.h194 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
384 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { in AddDefaultPred()
389 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { in AddDefaultCC()
394 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
400 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { in AddNoT1CC()
HDARMExpandPseudoInsts.cpp59 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
77 MachineInstrBuilder &UseMI, in TransferImpOps()
78 MachineInstrBuilder &DefMI) { in TransferImpOps()
389 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD()
454 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVST()
508 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandLaneOp()
592 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL()
663 MachineInstrBuilder LO16, HI16; in ExpandMOV32BitImm()
921 MachineInstrBuilder MIB = in ExpandMI()
933 MachineInstrBuilder MIB; in ExpandMI()
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HDThumbRegisterInfo.cpp165 MachineInstrBuilder MIB = in emitThumbRegPlusImmInReg()
306 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg); in emitThumbRegPlusImmediate()
323 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg); in emitThumbRegPlusImmediate()
361 MachineInstrBuilder MIB(*MBB.getParent(), &MI); in rewriteFrameIndex()
512 MachineInstrBuilder MIB(*MBB.getParent(), &MI); in eliminateFrameIndex()
HDARMInstrInfo.cpp121 MachineInstrBuilder MIB; in expandLoadStackGuard()
173 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, in runOnMachineFunction()
HDARMFastISel.cpp215 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
217 const MachineInstrBuilder &MIB,
262 const MachineInstrBuilder &
263 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { in AddOptionalDefs()
634 MachineInstrBuilder MIB; in ARMMaterializeGV()
655 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, in ARMMaterializeGV()
666 MachineInstrBuilder MIB; in ARMMaterializeGV()
914 const MachineInstrBuilder &MIB, in AddLoadStoreOperands()
1047 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, in ARMEmitLoad()
1168 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, in ARMEmitStore()
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HDARMBaseInstrInfo.cpp462 MachineInstrBuilder(*MI->getParent()->getParent(), MI) in PredicateInstruction()
667 MachineInstrBuilder MIB = in copyFromCPSR()
688 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); in copyToCPSR()
731 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
800 MachineInstrBuilder Mov; in copyPhysReg()
833 const MachineInstrBuilder &
834 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, in AddDReg()
882 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); in storeRegToStackSlot()
891 MachineInstrBuilder MIB = in storeRegToStackSlot()
926 MachineInstrBuilder MIB = in storeRegToStackSlot()
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HDThumb2InstrInfo.cpp156 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
197 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); in loadRegFromStackSlot()
334 MachineInstrBuilder MIB = in emitT2RegPlusImmediate()
473 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI); in rewriteT2FrameIndex()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDInstrEmitter.h25 class MachineInstrBuilder; variable
52 MachineInstrBuilder &MIB,
65 void AddRegisterOperand(MachineInstrBuilder &MIB,
76 void AddOperand(MachineInstrBuilder &MIB,
HDInstrEmitter.cpp207 MachineInstrBuilder &MIB, in CreateVirtualRegisters()
311 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand()
373 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, in AddOperand()
556 MachineInstrBuilder MIB = in EmitSubregNode()
613 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); in EmitRegSequence()
669 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); in EmitDbgValue()
784 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); in EmitMachineNode()
940 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), in EmitSpecialNode()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600InstrInfo.h30 class MachineInstrBuilder; variable
40 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
46 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
222 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
227 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
241 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
HDAMDGPUInstrInfo.h38 class MachineInstrBuilder; variable
173 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
181 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
HDR600InstrInfo.cpp1022 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); in PredicateInstruction()
1030 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); in PredicateInstruction()
1105 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, in buildIndirectWrite()
1112 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, in buildIndirectWrite()
1129 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV, in buildIndirectWrite()
1137 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, in buildIndirectRead()
1144 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, in buildIndirectRead()
1161 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV, in buildIndirectRead()
1175 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB, in buildDefaultInstruction()
1181 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode), in buildDefaultInstruction()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrBuilder.h32 static inline const MachineInstrBuilder&
33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMips16InstrInfo.cpp84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
171 static void addSaveRestoreRegs(MachineInstrBuilder &MIB, in addSaveRestoreRegs()
204 MachineInstrBuilder MIB; in makeFrame()
234 MachineInstrBuilder MIB; in restoreFrame()
274 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
276 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
278 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
281 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16), in adjustStackPtrBig()
HDMipsInstrInfo.cpp102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr()
277 MachineInstrBuilder
280 MachineInstrBuilder MIB; in genInstrWithNewOpc()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrBuilder.h26 static inline const MachineInstrBuilder &
27 addFrameReference(const MachineInstrBuilder &MIB, int FI) { in addFrameReference()
HDSystemZElimCompare.cpp203 MachineInstrBuilder(*Branch->getParent()->getParent(), Branch) in convertToBRCT()
220 MachineInstrBuilder(*MI->getParent()->getParent(), MI) in convertToLoadAndTest()
406 MachineInstrBuilder(*Branch->getParent()->getParent(), Branch) in fuseCompareAndBranch()
HDSystemZFrameLowering.cpp111 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, in addSavedGPR()
177 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG)); in spillCalleeSavedRegisters()
247 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG)); in restoreCalleeSavedRegisters()
/NextBSD/contrib/llvm/lib/CodeGen/
HDMachineSSAUpdater.cpp114 MachineInstrBuilder InsertNewDef(unsigned Opcode, in InsertNewDef()
188 MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB, in GetValueInMiddleOfBlock()
310 MachineInstrBuilder(*Pred->getParent(), PHI).addReg(Val).addMBB(Pred); in AddPHIOperand()

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