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Searched refs:MaskedValueIsZero (Results 1 – 25 of 28) sorted by relevance

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/NextBSD/contrib/llvm/lib/Transforms/InstCombine/
HDInstCombineShifts.cpp94 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
134 if (IC.MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
159 if (IC.MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
712 MaskedValueIsZero(I.getOperand(0), in visitShl()
771 MaskedValueIsZero(Op0, APInt::getLowBitsSet(Op1C->getBitWidth(), ShAmt), in visitLShr()
816 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt), in visitAShr()
824 if (MaskedValueIsZero(Op0, in visitAShr()
HDInstCombineMulDivRem.cpp370 if (MaskedValueIsZero(Op0, Negative2, 0, &I)) in visitMul()
372 else if (MaskedValueIsZero(Op1, Negative2, 0, &I)) in visitMul()
1154 if (MaskedValueIsZero(Op0, Mask, 0, &I)) { in visitSDiv()
1155 if (MaskedValueIsZero(Op1, Mask, 0, &I)) { in visitSDiv()
1435 if (MaskedValueIsZero(Op1, Mask, 0, &I) && in visitSRem()
1436 MaskedValueIsZero(Op0, Mask, 0, &I)) { in visitSRem()
HDInstCombineAndOrXor.cpp396 if (MaskedValueIsZero(RHS, Mask, 0, &I)) in FoldLogicalPlusAnd()
1243 if (MaskedValueIsZero(Op0LHS, NotAndRHS, 0, &I)) { in visitAnd()
1250 MaskedValueIsZero(Op0RHS, NotAndRHS, 0, &I)) { in visitAnd()
1283 if (MaskedValueIsZero(Op0LHS, Mask, 0, &I)) { in visitAnd()
2214 MaskedValueIsZero(Op1, C1->getValue(), 0, &I)) { in visitOr()
2223 MaskedValueIsZero(Op0, C1->getValue(), 0, &I)) { in visitOr()
2262 MaskedValueIsZero(V2, ~C1->getValue(), 0, &I)) || // (V|N) in visitOr()
2264 MaskedValueIsZero(V1, ~C1->getValue(), 0, &I)))) // (N|V) in visitOr()
2270 MaskedValueIsZero(V2, ~C2->getValue(), 0, &I)) || // (V|N) in visitOr()
2272 MaskedValueIsZero(V1, ~C2->getValue(), 0, &I)))) // (N|V) in visitOr()
[all …]
HDInstCombineInternal.h470 bool MaskedValueIsZero(Value *V, const APInt &Mask, unsigned Depth = 0,
472 return llvm::MaskedValueIsZero(V, Mask, DL, Depth, AC, CxtI, DT);
HDInstCombineCasts.cpp372 if (IC.MaskedValueIsZero(I->getOperand(0), Mask, 0, CxtI) && in CanEvaluateTruncated()
373 IC.MaskedValueIsZero(I->getOperand(1), Mask, 0, CxtI)) { in CanEvaluateTruncated()
396 if (IC.MaskedValueIsZero(I->getOperand(0), in CanEvaluateTruncated()
703 if (IC.MaskedValueIsZero(I->getOperand(1), in CanEvaluateZExtd()
805 if (MaskedValueIsZero(Res, in visitZExt()
HDInstCombineAddSub.cpp1097 if (!MaskedValueIsZero(XorLHS, Mask, 0, &I)) in visitAdd()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreSelectionDAGInfo.cpp29 DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { in EmitTargetCodeForMemcpy()
HDXCoreISelLowering.cpp693 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && in TryExpandADDWithMul()
694 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { in TryExpandADDWithMul()
1798 DAG.MaskedValueIsZero(Mul0, HighMask) && in PerformDAGCombine()
1799 DAG.MaskedValueIsZero(Mul1, HighMask) && in PerformDAGCombine()
1800 DAG.MaskedValueIsZero(Addend0, HighMask) && in PerformDAGCombine()
1801 DAG.MaskedValueIsZero(Addend1, HighMask)) { in PerformDAGCombine()
/NextBSD/contrib/llvm/include/llvm/Analysis/
HDValueTracking.h94 bool MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelDAGToDAG.cpp229 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { in MatchAddress()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZOperators.td504 return CurDAG->MaskedValueIsZero(N->getOperand(0),
512 return CurDAG->MaskedValueIsZero(N->getOperand(1),
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDTargetLowering.cpp1547 if (DAG.MaskedValueIsZero(N0, in SimplifySetCC()
1917 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) in SimplifySetCC()
2903 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && in expandMUL()
2904 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { in expandMUL()
HDDAGCombiner.cpp2870 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { in visitANDLike()
2935 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), in visitAND()
2951 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { in visitAND()
3163 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, in visitAND()
3183 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, in visitAND()
3299 !DAG.MaskedValueIsZero( in MatchBSwapHWordLow()
3532 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && in visitORLike()
3533 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { in visitORLike()
3661 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) in visitOR()
4291 if (DAG.MaskedValueIsZero(SDValue(N, 0), in visitSHL()
[all …]
HDSelectionDAG.cpp2005 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); in SignBitIsZero()
2011 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, in MaskedValueIsZero() function in SelectionDAG
2749 !MaskedValueIsZero(Op.getOperand(0), in isBaseWithConstantOffset()
HDSelectionDAGISel.cpp1680 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) in CheckAndMask()
/NextBSD/contrib/llvm/lib/Analysis/
HDValueTracking.cpp188 static bool MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
191 bool llvm::MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL, in MaskedValueIsZero() function in llvm
194 return ::MaskedValueIsZero(V, Mask, DL, Depth, in MaskedValueIsZero()
1891 bool MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL, in MaskedValueIsZero() function
HDInstructionSimplify.cpp1815 MaskedValueIsZero(V2, C2->getValue(), Q.DL, 0, Q.AC, Q.CxtI, Q.DT)) in SimplifyOrInst()
1818 MaskedValueIsZero(V1, C2->getValue(), Q.DL, 0, Q.AC, Q.CxtI, Q.DT)) in SimplifyOrInst()
1826 MaskedValueIsZero(V2, C1->getValue(), Q.DL, 0, Q.AC, Q.CxtI, Q.DT)) in SimplifyOrInst()
1829 MaskedValueIsZero(V1, C1->getValue(), Q.DL, 0, Q.AC, Q.CxtI, Q.DT)) in SimplifyOrInst()
HDBasicAliasAnalysis.cpp216 if (!MaskedValueIsZero(BOp->getOperand(0), RHSC->getValue(), DL, 0, AC, in GetLinearExpression()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp1703 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) && in LowerUDIVREM64()
1704 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) { in LowerUDIVREM64()
1771 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) && in LowerUDIVREM()
1772 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) { in LowerUDIVREM()
HDSIISelLowering.cpp1433 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) { in performUCharToFloatCombine()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDSelectionDAG.h1164 bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp9405 if (!DAG.MaskedValueIsZero(N->getOperand(0), in DAGCombineTruncBoolExt()
9407 !DAG.MaskedValueIsZero(N->getOperand(1), in DAGCombineTruncBoolExt()
9793 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0), in DAGCombineExtBoolTrunc()
10367 if (DAG.MaskedValueIsZero( in PerformDAGCombine()
HDPPCISelDAGToDAG.cpp3110 if (!CurDAG->MaskedValueIsZero(Op0, in combineToCMPB()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrCompiler.td1158 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp8686 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && in PerformORCombine()
9864 DAG.MaskedValueIsZero(N0.getOperand(0), in PerformShiftCombine()

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