Home
last modified time | relevance | path

Searched refs:NumVecs (Results 1 – 5 of 5) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelDAGToDAG.cpp219 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
227 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
235 bool isUpdating, unsigned NumVecs,
241 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
247 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
279 SDValue GetVLDSTAlign(SDValue Align, SDLoc dl, unsigned NumVecs,
1683 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1684 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1685 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1803 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD() argument
[all …]
HDARMISelLowering.cpp9066 unsigned NumVecs = 0; in CombineBaseUpdate() local
9072 NumVecs = 1; break; in CombineBaseUpdate()
9074 NumVecs = 2; break; in CombineBaseUpdate()
9076 NumVecs = 3; break; in CombineBaseUpdate()
9078 NumVecs = 4; break; in CombineBaseUpdate()
9080 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
9082 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
9084 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
9086 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
9088 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelDAGToDAG.cpp138 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
142 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
144 SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
146 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
147 SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
149 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
150 SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
151 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
152 SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
960 SDNode *AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, in SelectTable() argument
[all …]
HDAArch64ISelLowering.cpp8358 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
8363 NumVecs = 2; break; in performNEONPostLDSTCombine()
8365 NumVecs = 3; break; in performNEONPostLDSTCombine()
8367 NumVecs = 4; break; in performNEONPostLDSTCombine()
8369 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
8371 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
8373 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
8375 NumVecs = 2; break; in performNEONPostLDSTCombine()
8377 NumVecs = 3; break; in performNEONPostLDSTCombine()
8379 NumVecs = 4; break; in performNEONPostLDSTCombine()
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp24748 unsigned NumVecs = VT.getSizeInBits() / 128; in PerformSExtCombine() local
24754 for (unsigned i = 0, Offset = 0; i != NumVecs; in PerformSExtCombine()