Searched refs:Op5 (Results 1 – 5 of 5) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/XCore/Disassembler/ |
| HD | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL6RInstruction()
682 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL5RInstruction()
|
| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonExpandPredSpillCode.cpp | 148 MachineOperand &Op5 = MI->getOperand(5); in runOnMachineFunction() local
158 NewMI->addOperand(Op5); in runOnMachineFunction()
|
| /NextBSD/contrib/llvm/lib/Target/ARM/AsmParser/ |
| HD | ARMAsmParser.cpp | 5493 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm() local
5498 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
5501 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
5503 Op5.isImm() && !Op5.isImm0_508s4()); in tryConvertingToTwoOperandForm()
5524 const ARMOperand *LastOp = &Op5; in tryConvertingToTwoOperandForm()
5526 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && in tryConvertingToTwoOperandForm()
5552 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|
| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | SelectionDAG.h | 917 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAG.cpp | 5647 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
5648 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|