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Searched refs:P0 (Results 1 – 25 of 30) sorted by relevance

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/NextBSD/contrib/llvm/include/llvm/ADT/
HDVariadicFunction.h154 ResultT operator()(Param0T P0) const { in operator()
155 return Func(P0, None); in operator()
159 ResultT operator()(Param0T P0, LLVM_COMMA_JOIN ## N(const ArgT &A)) const { \
161 return Func(P0, makeArrayRef(Args)); \
201 ResultT operator()(Param0T P0, Param1T P1) const { in operator()
202 return Func(P0, P1, None); in operator()
206 ResultT operator()(Param0T P0, Param1T P1, \
209 return Func(P0, P1, makeArrayRef(Args)); \
250 ResultT operator()(Param0T P0, Param1T P1, Param2T P2) const { in operator()
251 return Func(P0, P1, P2, None); in operator()
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/NextBSD/contrib/gcc/config/arm/
HDvfp.md163 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
167 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
169 return \"fldd%?\\t%P0, %1\\t%@ int\";
222 return \"fmdrr%?\\t%P0, %Q1, %R1\";
228 return \"fldd%?\\t%P0, %1\";
232 return \"fcpyd%?\\t%P0, %P1\";
281 fcpyd%D3\\t%P0, %P2
282 fcpyd%d3\\t%P0, %P1
283 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
284 fmdrr%D3\\t%P0, %Q2, %R2
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/NextBSD/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonMCCompound.cpp103 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
116 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
147 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
162 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg) in getCompoundCandidateGroup()
185 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || in getCompoundOp()
193 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; in getCompoundOp()
195 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; in getCompoundOp()
197 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; in getCompoundOp()
199 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; in getCompoundOp()
HDHexagonMCDuplexInfo.cpp295 if ((HexagonMCInstrInfo::isPredReg(SrcReg) && (Hexagon::P0 == SrcReg)) && in getDuplexCandidateGroup()
313 if (Hexagon::P0 == SrcReg) { in getDuplexCandidateGroup()
494 Hexagon::P0 == PredReg && MCI.getOperand(2).isImm() && in getDuplexCandidateGroup()
503 if (Hexagon::P0 == DstReg && in getDuplexCandidateGroup()
HDHexagonMCInstrInfo.cpp385 return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0); in isPredReg()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonIsetDx.td32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBr…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
93 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasN…
122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBran…
180 let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
409 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, ha…
536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPr…
547 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewVal…
599 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBra…
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HDHexagonRegisterInfo.td110 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>;
132 def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>,
201 P0, P1, P2, P3,
HDHexagonInstrInfoV3.td265 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
HDHexagonInstrInfoV4.td4050 let Defs = [PC, P0], Uses = [P0] in {
4101 let Defs = [PC, P0], Uses = [P0] in {
4155 let Defs = [PC, P0], Uses = [P0] in {
4209 let Defs = [PC, P0], Uses = [P0] in {
/NextBSD/lib/msun/src/
HDs_cbrt.c30 P0 = 1.87595182427177009643, /* 0x3ffe03e6, 0x0f61e692 */ variable
89 t=t*((P0+r*(P1+r*P2))+((r*r)*r)*(P3+r*P4)); in cbrt()
/NextBSD/share/syscons/fonts/
HDiso-thin-8x16.fnt44 M/$)`/`)"/````````!`0$'P0$!`0$`X```````````!"0D)"0D(]````````
46 M````````0D)"0D)"/@("/````````'X$"!`@0'X```````P0$!`0(!`0$!`,
HDiso15-thin-8x16.fnt44 M/$)`/`)"/````````!`0$'P0$!`0$`X```````````!"0D)"0D(]````````
46 M````````0D)"0D)"/@("/````````'X$"!`@0'X```````P0$!`0(!`0$!`,
HDiso04-wide-8x16.fnt71 M`-S^YL;&QL;&!AP``'P0.'SNQL;^QL;&QL8```P8(#A\[L;&_L;&QL;&```X
HDiso04-vga9-wide-8x16.fnt49 MQL;^QL;&QL8``#AL$#A\[L;&_L;&QL;&``!VW!`X?.[&QO[&QL;&Q@``;&P0
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMips64InstrInfo.td376 let Defs = [HI0, LO0, P0, P1, P2] in
389 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
390 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
391 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
392 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
407 let Defs = [P0, P1, P2] in
412 let Defs = [MPL0, P0, P1, P2] in
417 let Defs = [MPL1, MPL2, P0, P1, P2] in
HDMipsRegisterInfo.td267 def P0 : MipsReg<0, "p0">;
453 def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ScheduleAtom.td28 // P0 only
29 // InstrItinData<class, [InstrStage<N, [P0]>] >,
30 // P0 or P1
31 // InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
32 // P0 and P1
33 // InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
HDX86SchedHaswell.td274 // Starting with P0.
/NextBSD/lib/msun/bsdsrc/
HDb_tgamma.c97 #define P0 6.21389571821820863029017800727e-01 macro
255 p = P0 + z*(P1 + z*(P2 + z*(P3 + z*P4)));
/NextBSD/contrib/gcc/config/ia64/
HDvect.md51 st8%Q0 %0 = %r1%P0
54 stf8 %0 = %1%P0
868 "%,stf8 %0 = %1%P0",
873 "%,st8%Q0 %0 = %r1%P0",
HDia64.md233 st1%Q0 %0 = %1%P0
282 st1%Q0 %0 = %r1%P0
307 st2%Q0 %0 = %r1%P0
333 st4%Q0 %0 = %r1%P0
365 "%,st8%Q0 %0 = %r1%P0",
370 "%,stf8 %0 = %1%P0",
903 stfs %0 = %F1%P0
908 st4%Q0 %0 = %1%P0"
929 stfd %0 = %F1%P0
934 st8%Q0 %0 = %1%P0"
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/NextBSD/contrib/llvm/lib/Transforms/Vectorize/
HDSLPVectorizer.cpp1191 CmpInst::Predicate P0 = cast<CmpInst>(VL0)->getPredicate(); in buildTree_rec() local
1195 if (Cmp->getPredicate() != P0 || in buildTree_rec()
2209 CmpInst::Predicate P0 = cast<CmpInst>(VL0)->getPredicate(); in vectorizeTree() local
2212 V = Builder.CreateFCmp(P0, L, R); in vectorizeTree()
2214 V = Builder.CreateICmp(P0, L, R); in vectorizeTree()
/NextBSD/sys/gnu/dts/arm/
HDam43x-epos-evm.dts306 0x03010200 /* P0 */
/NextBSD/contrib/llvm/lib/Target/Hexagon/Disassembler/
HDHexagonDisassembler.cpp108 static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
/NextBSD/contrib/gcc/config/i386/
HDi386.md1259 movabs{l}\t{%1, %P0|%P0, %1}
1377 movabs{w}\t{%1, %P0|%P0, %1}
1713 movabs{b}\t{%1, %P0|%P0, %1}
2074 movabs{q}\t{%1, %P0|%P0, %1}
14155 return "jmp\t%P0";
14157 return "call\t%P0";
14171 return "jmp\t%P0";
14173 return "call\t%P0";
14208 return "jmp\t%P0";
14210 return "call\t%P0";
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