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Searched refs:PredReg (Results 1 – 22 of 22) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMLoadStoreOptimizer.cpp128 ARMCC::CondCodes Pred, unsigned PredReg);
131 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
135 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
432 ARMCC::CondCodes Pred, unsigned PredReg) { in UpdateBaseRegUses() argument
500 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
518 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
567 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, in CreateLoadStoreMulti() argument
681 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
691 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
696 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
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HDThumb2InstrInfo.cpp60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
223 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
228 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
245 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
252 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
261 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
272 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
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HDThumbRegisterInfo.cpp66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() argument
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() argument
106 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
113 PredReg, MIFlags); in emitLoadConstPool()
116 PredReg, MIFlags); in emitLoadConstPool()
HDMLxExpansionPass.cpp285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
298 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
310 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
HDARMBaseRegisterInfo.cpp397 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
408 .addImm(0).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
747 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
755 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
759 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
HDThumb2SizeReduction.cpp582 unsigned PredReg = 0; in ReduceSpecial() local
583 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
686 unsigned PredReg = 0; in ReduceTo2Addr() local
687 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
783 unsigned PredReg = 0; in ReduceToNarrow() local
784 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
HDARMBaseInstrInfo.h439 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
460 ARMCC::CondCodes Pred, unsigned PredReg,
466 ARMCC::CondCodes Pred, unsigned PredReg,
HDThumb2ITBlockPass.cpp184 unsigned PredReg = 0; in InsertITInstructions() local
185 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
HDThumbRegisterInfo.h43 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
HDThumb2InstrInfo.h73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
HDARMFrameLowering.cpp128 unsigned PredReg = 0) { in emitRegPlusImmediate() argument
131 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
134 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
142 unsigned PredReg = 0) { in emitSPUpdate() argument
144 MIFlags, Pred, PredReg); in emitSPUpdate()
1802 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1804 Pred, PredReg); in eliminateCallFramePseudoInstr()
1807 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
1810 Pred, PredReg); in eliminateCallFramePseudoInstr()
HDARMBaseRegisterInfo.h164 unsigned PredReg = 0,
HDARMConstantIslandPass.cpp1455 unsigned PredReg = 0; in createNewWater() local
1456 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1462 DEBUG(unsigned PredReg; in createNewWater()
1463 assert(!isThumb || getITInstrPredicate(MI, PredReg) == ARMCC::AL)); in createNewWater()
1911 unsigned PredReg = 0; in optimizeThumb2Branches() local
1912 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
1930 Pred = getInstrPredicate(CmpMI, PredReg); in optimizeThumb2Branches()
HDARMExpandPseudoInsts.cpp656 unsigned PredReg = 0; in ExpandMOV32BitImm() local
657 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); in ExpandMOV32BitImm()
684 LO16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
685 HI16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
733 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
734 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
HDARMBaseInstrInfo.cpp1668 unsigned PredReg = 0; in isProfitableToIfCvt() local
1669 ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg); in isProfitableToIfCvt()
1724 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate() argument
1727 PredReg = 0; in getInstrPredicate()
1731 PredReg = MI->getOperand(PIdx+1).getReg(); in getInstrPredicate()
1754 unsigned PredReg = 0; in commuteInstruction() local
1755 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstruction()
1757 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstruction()
1945 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate() argument
1950 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitARMRegPlusImmediate()
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HDARMISelDAGToDAG.cpp2532 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2533 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; in Select()
2802 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2803 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2822 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2823 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2841 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2842 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
/NextBSD/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonMCCompound.cpp183 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
185 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || in getCompoundOp()
186 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); in getCompoundOp()
193 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; in getCompoundOp()
195 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; in getCompoundOp()
197 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; in getCompoundOp()
199 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; in getCompoundOp()
HDHexagonMCDuplexInfo.cpp182 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
492 PredReg = MCI.getOperand(1).getReg(); // P0 in getDuplexCandidateGroup()
494 Hexagon::P0 == PredReg && MCI.getOperand(2).isImm() && in getDuplexCandidateGroup()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonGenPredicate.cpp97 bool isScalarPred(Register PredReg);
304 bool HexagonGenPredicate::isScalarPred(Register PredReg) { in isScalarPred() argument
306 WorkQ.push(PredReg); in isScalarPred()
HDHexagonInstrInfo.cpp1043 unsigned PredReg, PredRegPos, PredRegFlags; in PredicateInstruction() local
1044 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags); in PredicateInstruction()
1047 T.addReg(PredReg, PredRegFlags); in PredicateInstruction()
1061 MRI.clearKillFlags(PredReg); in PredicateInstruction()
1997 unsigned &PredReg, unsigned &PredRegPos, in getPredReg() argument
2006 PredReg = Cond[1].getReg(); in getPredReg()
HDHexagonInstrInfo.h226 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
HDHexagonHardwareLoops.cpp613 unsigned PredReg, PredPos, PredRegFlags; in getLoopTripCount() local
614 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) in getLoopTripCount()
616 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()