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Searched refs:RO (Results 1 – 25 of 44) sorted by relevance

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/NextBSD/contrib/ntp/libparse/
HDinfo_trimble.c56 { CMD_RDATAA, "CMD_RDATAA", "data channel A configuration (0x3D)", "trimble_channelA", RO },
57 { CMD_RALMANAC, "CMD_RALMANAC", "almanac data for sat (0x40)", "gps_almanac", RO },
58 { CMD_RCURTIME, "CMD_RCURTIME", "GPS time (0x41)", "gps_time", RO },
59 …{ CMD_RSPOSXYZ, "CMD_RSPOSXYZ", "single precision XYZ position (0x42)", "gps_position(XYZ)", RO|DE…
60 { CMD_RVELOXYZ, "CMD_RVELOXYZ", "velocity fix (XYZ ECEF) (0x43)", "gps_velocity(XYZ)", RO|DEF },
61 { CMD_RBEST4, "CMD_RBEST4", "best 4 satellite selection (0x44)", "trimble_best4", RO|DEF },
62 { CMD_RVERSION, "CMD_RVERSION", "software version (0x45)", "trimble_version", RO|DEF },
63 …{ CMD_RRECVHEALTH, "CMD_RRECVHEALTH", "receiver health (0x46)", "trimble_receiver_health", RO|DEF …
64 …SIGNALLV, "CMD_RSIGNALLV", "signal levels of all satellites (0x47)", "trimble_signal_levels", RO },
65 { CMD_RMESSAGE, "CMD_RMESSAGE", "GPS system message (0x48)", "gps-message", RO|DEF },
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMicroMipsInstrInfo.td167 RegisterOperand RO> :
168 InstSE<(outs), (ins RO:$rs, opnd:$offset),
177 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
179 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
181 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
187 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
189 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
191 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
210 class MovePMM16<string opstr, RegisterOperand RO> :
211 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
[all …]
HDMipsInstrInfo.td601 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
604 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
606 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
613 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
617 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
619 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
635 class LogicNOR<string opstr, RegisterOperand RO>:
636 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
638 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
644 RegisterOperand RO, InstrItinClass itin,
[all …]
HDMips64InstrInfo.td311 class Count1s<string opstr, RegisterOperand RO>:
312 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
313 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
344 RegisterOperand RO, bits<64> shift = 1> :
345 InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset),
347 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
355 class MFC2OP<string asmstr, RegisterOperand RO> :
356 InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
624 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
625 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
HDMipsDSPInstrInfo.td320 ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
321 dag OutOperandList = (outs RO:$rd);
324 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
329 InstrItinClass itin, RegisterOperand RO> {
330 dag OutOperandList = (outs RO:$rd);
331 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
333 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
339 RegisterOperand RO> {
340 dag OutOperandList = (outs RO:$rd);
341 dag InOperandList = (ins RO:$rt, uimm16:$rs_sa);
[all …]
HDMipsInstrFPU.td530 class BuildPairF64Base<RegisterOperand RO> :
531 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
532 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
541 class ExtractElementF64Base<RegisterOperand RO> :
542 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
543 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
/NextBSD/contrib/ntp/ntpd/
HDntp_control.c335 { CS_STRATUM, RO, "stratum" }, /* 2 */
336 { CS_PRECISION, RO, "precision" }, /* 3 */
337 { CS_ROOTDELAY, RO, "rootdelay" }, /* 4 */
338 { CS_ROOTDISPERSION, RO, "rootdisp" }, /* 5 */
339 { CS_REFID, RO, "refid" }, /* 6 */
340 { CS_REFTIME, RO, "reftime" }, /* 7 */
341 { CS_POLL, RO, "tc" }, /* 8 */
342 { CS_PEERID, RO, "peer" }, /* 9 */
343 { CS_OFFSET, RO, "offset" }, /* 10 */
344 { CS_DRIFT, RO, "frequency" }, /* 11 */
[all …]
HDrefclock_neoclock4x.c738 tt = add_var(&out->kv_list, sizeof(tmpbuf)-1, RO|DEF); in neoclock4x_control()
741 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
743 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
745 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
747 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
754 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
761 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
768 tt = add_var(&out->kv_list, 80, RO|DEF); in neoclock4x_control()
770 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
772 tt = add_var(&out->kv_list, 80, RO|DEF); in neoclock4x_control()
[all …]
HDrefclock_parse.c3556 tt = add_var(&out->kv_list, 80, RO); in parse_control()
3563 tt = add_var(&out->kv_list, 80, RO|DEF); in parse_control()
3567 start = tt = add_var(&out->kv_list, 128, RO|DEF); in parse_control()
3587 start = tt = add_var(&out->kv_list, 512, RO|DEF); in parse_control()
3619 start = tt = add_var(&out->kv_list, 80, RO|DEF); in parse_control()
3636 start = tt = add_var(&out->kv_list, LEN_STATES, RO|DEF); in parse_control()
3681 tt = add_var(&out->kv_list, 32, RO); in parse_control()
3684 tt = add_var(&out->kv_list, 80, RO); in parse_control()
3687 tt = add_var(&out->kv_list, 128, RO); in parse_control()
4333 set_var(&parse->kv, buffer, strlen(buffer)+1, RO|DEF); in gps16x_message()
[all …]
/NextBSD/sys/dev/aic7xxx/
HDaic79xx.reg216 access_mode RO
290 access_mode RO
433 access_mode RO
458 access_mode RO
639 access_mode RO
650 access_mode RO
661 access_mode RO
687 access_mode RO
697 access_mode RO
707 access_mode RO
[all …]
HDaic7xxx.reg108 access_mode RO
281 access_mode RO
314 access_mode RO
330 access_mode RO
346 access_mode RO
423 access_mode RO
633 access_mode RO
639 access_mode RO
651 access_mode RO
658 access_mode RO
[all …]
/NextBSD/sys/boot/fdt/dts/powerpc/
HDp1020rdb.dts100 label = "NOR (RO) Vitesse-7385 Firmware";
107 label = "NOR (RO) DTB Image";
114 label = "NOR (RO) Linux Kernel Image";
129 label = "NOR (RO) U-Boot Image";
145 label = "NAND (RO) U-Boot Image";
152 label = "NAND (RO) DTB Image";
159 label = "NAND (RO) Linux Kernel Image";
166 label = "NAND (RO) Compressed RFS Image";
289 label = "SPI (RO) U-Boot Image";
296 label = "SPI (RO) DTB Image";
[all …]
/NextBSD/sys/arm/conf/
HDSAM9260EK.hints6 # Area 0: 00000000 to 000041FF (RO) Bootstrap
8 # Area 2: 00008400 to 00041FFF (RO) U-Boot
HDHL201.hints6 # Area 0: 00000000 to 000041FF (RO) Bootstrap
8 # Area 2: 00008400 to 00041FFF (RO) U-Boot
/NextBSD/contrib/llvm/lib/Analysis/
HDScalarEvolutionNormalization.cpp215 const SCEV *RO = X->getRHS(); in TransformImpl() local
217 const SCEV *RN = TransformSubExpr(RO, User, OperandValToReplace); in TransformImpl()
218 if (LO != LN || RO != RN) in TransformImpl()
/NextBSD/usr.sbin/cron/doc/
HDMAIL12 Status: RO
30 Status: RO
56 Status: RO
85 Status: RO
97 Status: RO
111 Status: RO
130 Status: RO
159 Status: RO
207 Status: RO
231 Status: RO
[all …]
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonGenInsert.cpp364 OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {} in OrderedRegisterList() argument
486 void buildOrderingMF(RegisterOrdering &RO) const;
487 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
554 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const { in buildOrderingMF()
570 RO.insert(std::make_pair(R, Index++)); in buildOrderingMF()
582 RegisterOrdering &RO) const { in buildOrderingBT()
594 RO.insert(std::make_pair(VRs[i], i)); in buildOrderingBT()
HDHexagonInstrInfo.cpp224 const MachineOperand &RO = Cond[1]; in InsertBranch() local
225 unsigned Flags = getUndefRegState(RO.isUndef()); in InsertBranch()
226 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); in InsertBranch()
247 const MachineOperand &RO = Cond[1]; in InsertBranch() local
248 unsigned Flags = getUndefRegState(RO.isUndef()); in InsertBranch()
249 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); in InsertBranch()
HDHexagonExpandCondsets.cpp170 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
940 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, in renameInRange() argument
954 if (!Op.isReg() || RO != RegisterRef(Op)) in renameInRange()
/NextBSD/contrib/llvm/utils/TableGen/
HDAsmWriterEmitter.cpp852 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; in EmitPrintAliasInstruction() local
854 switch (RO.Kind) { in EmitPrintAliasInstruction()
856 const Record *Rec = RO.getRecord(); in EmitPrintAliasInstruction()
857 StringRef ROName = RO.getName(); in EmitPrintAliasInstruction()
939 MIOpNum += RO.getMINumOperands(); in EmitPrintAliasInstruction()
/NextBSD/sys/dev/aic7xxx/aicasm/
HDaicasm_symbol.h65 RO = 0x01, enumerator
HDaicasm_scan.l174 else if (strcmp(yytext, "RO") == 0)
/NextBSD/contrib/llvm/tools/llvm-diff/
HDDifferenceEngine.cpp354 Value *LO = L->getOperand(I), *RO = R->getOperand(I); in diff() local
355 if (!equivalentAsOperands(LO, RO)) { in diff()
356 if (Complain) Engine.logf("operands %l and %r differ") << LO << RO; in diff()
/NextBSD/crypto/openssl/crypto/dh/
HDexample24 Status: RO
/NextBSD/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/
HDRegionStore.cpp112 const RegionOffset &RO = R->getAsOffset(); in Make() local
113 if (RO.hasSymbolicOffset()) in Make()
114 return BindingKey(cast<SubRegion>(R), cast<SubRegion>(RO.getRegion()), k); in Make()
116 return BindingKey(RO.getRegion(), RO.getOffset(), k); in Make()

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