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Searched refs:Reg1 (Results 1 – 25 of 27) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/AArch64/MCTargetDesc/
HDAArch64AsmBackend.cpp371 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
388 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
391 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
394 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
397 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
400 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
403 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
407 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
414 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
417 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/NextBSD/contrib/llvm/include/llvm/MC/
HDMCRegisterInfo.h76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
600 uint16_t Reg1; variable
602 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} in MCRegUnitRootIterator()
606 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
622 Reg0 = Reg1;
623 Reg1 = 0;
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64FrameLowering.cpp747 unsigned Reg1 = CSI[idx].getReg(); in spillCalleeSavedRegisters() local
769 if (AArch64::GPR64RegClass.contains(Reg1)) { in spillCalleeSavedRegisters()
777 } else if (AArch64::FPR64RegClass.contains(Reg1)) { in spillCalleeSavedRegisters()
787 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", " in spillCalleeSavedRegisters()
799 MBB.addLiveIn(Reg1); in spillCalleeSavedRegisters()
802 .addReg(Reg1, getPrologueDeath(MF, Reg1)) in spillCalleeSavedRegisters()
824 unsigned Reg1 = CSI[i].getReg(); in restoreCalleeSavedRegisters() local
842 if (AArch64::GPR64RegClass.contains(Reg1)) { in restoreCalleeSavedRegisters()
849 } else if (AArch64::FPR64RegClass.contains(Reg1)) { in restoreCalleeSavedRegisters()
858 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", " in restoreCalleeSavedRegisters()
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsAsmPrinter.h73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
HDMipsAsmPrinter.cpp792 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
801 unsigned Temp = Reg1; in EmitInstrRegReg()
802 Reg1 = Reg2; in EmitInstrRegReg()
806 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
812 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
816 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
823 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
827 unsigned temp = Reg1; in EmitMovFPIntPair()
828 Reg1 = Reg2; in EmitMovFPIntPair()
831 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
HDMips16InstrInfo.cpp265 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
274 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
278 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
279 MIB3.addReg(Reg1); in adjustStackPtrBig()
283 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
HDMipsSEFrameLowering.cpp430 unsigned Reg1 = in emitPrologue() local
434 std::swap(Reg0, Reg1); in emitPrologue()
442 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
447 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
450 std::swap(Reg0, Reg1); in emitPrologue()
458 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
HDMips16InstrInfo.h117 unsigned Reg1, unsigned Reg2) const;
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrBuilder.h116 unsigned Reg1, bool isKill1, in addRegReg() argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCRegisterInfo.cpp467 unsigned Reg1 = Reg; in lowerCRSpilling() local
472 .addReg(Reg1, RegState::Kill) in lowerCRSpilling()
512 unsigned Reg1 = Reg; in lowerCRRestore() local
518 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
556 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
561 .addReg(Reg1, RegState::Kill) in lowerCRBitSpilling()
HDPPCVSXSwapRemoval.cpp801 unsigned Reg1 = MI->getOperand(1).getReg(); in handleSpecialSwappables() local
804 MI->getOperand(2).setReg(Reg1); in handleSpecialSwappables()
HDPPCInstrInfo.cpp290 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstruction() local
299 if (Reg0 == Reg1) { in commuteInstruction()
324 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstruction()
333 MI->getOperand(2).setReg(Reg1); in commuteInstruction()
/NextBSD/contrib/llvm/lib/Target/ARM/InstPrinter/
HDARMInstPrinter.cpp1460 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1464 printRegName(O, Reg1); in printVectorListTwo()
1473 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1477 printRegName(O, Reg1); in printVectorListTwoSpaced()
1528 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1532 printRegName(O, Reg1); in printVectorListTwoAllLanes()
1575 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
1579 printRegName(O, Reg1); in printVectorListTwoSpacedAllLanes()
/NextBSD/contrib/llvm/lib/CodeGen/
HDAggressiveAntiDepBreaker.h100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
HDTargetInstrInfo.cpp139 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() local
152 if (HasDef && Reg0 == Reg1 && in commuteInstruction()
160 Reg0 = Reg1; in commuteInstruction()
174 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
HDAggressiveAntiDepBreaker.cpp79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument
85 unsigned Group1 = GetGroup(Reg1); in UnionGroups()
HDRegisterCoalescer.cpp1907 unsigned Reg1; in valuesIdentical() local
1908 std::tie(Orig1, Reg1) = Other.followCopyChain(Value1); in valuesIdentical()
1914 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDA15SDOptimizer.cpp89 unsigned Reg1, unsigned Reg2);
469 unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
475 .addReg(Reg1) in createRegSequence()
HDThumb2SizeReduction.cpp643 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
648 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
654 if (Reg1 != Reg0) in ReduceTo2Addr()
661 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
HDARMFastISel.cpp2784 unsigned Reg1 = getRegForValue(Src1Value); in SelectShift() local
2785 if (Reg1 == 0) return false; in SelectShift()
2798 .addReg(Reg1); in SelectShift()
HDARMISelDAGToDAG.cpp3851 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in SelectInlineAsm() local
3875 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in SelectInlineAsm()
3890 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in SelectInlineAsm()
HDARMBaseInstrInfo.cpp2693 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate() local
2699 .addReg(Reg1, getKillRegState(isKill)) in FoldImmediate()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetRegisterInfo.h83 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
84 return MC->contains(Reg1, Reg2); in contains()
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenRegisters.cpp1122 for (const auto &Reg1 : Registers) { in computeComposites() local
1124 if (TopoSigs.test(Reg1.getTopoSig())) in computeComposites()
1126 TopoSigs.set(Reg1.getTopoSig()); in computeComposites()
1128 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); in computeComposites()
1134 if (&Reg1 == Reg2) in computeComposites()
1146 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
/NextBSD/contrib/llvm/lib/MC/
HDMCDwarf.cpp1047 unsigned Reg1 = Instr.getRegister(); in EmitCFIInstruction() local
1050 Reg1 = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg1, true), false); in EmitCFIInstruction()
1054 Streamer.EmitULEB128IntValue(Reg1); in EmitCFIInstruction()

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