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Searched refs:RegList (Results 1 – 17 of 17) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMCallingConv.h31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
34 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
49 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
204 ArrayRef<uint16_t> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
207 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
208 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
213 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
214 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
219 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
222 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
[all …]
HDARMBaseRegisterInfo.cpp66 const MCPhysReg *RegList = in getCalleeSavedRegs() local
90 return RegList; in getCalleeSavedRegs()
HDARMAsmPrinter.cpp1088 SmallVector<unsigned, 4> RegList; in EmitUnwindingInstruction() local
1113 RegList.push_back(MO.getReg()); in EmitUnwindingInstruction()
1121 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1125 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
HDARMBaseInstrInfo.cpp2037 SmallVector<MachineOperand, 4> RegList; in tryFoldSPUpdateIntoPushPop() local
2039 RegList.push_back(MI->getOperand(i)); in tryFoldSPUpdateIntoPushPop()
2051 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, in tryFoldSPUpdateIntoPushPop()
2075 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, in tryFoldSPUpdateIntoPushPop()
2091 for (int i = RegList.size() - 1; i >= 0; --i) in tryFoldSPUpdateIntoPushPop()
2092 MIB.addOperand(RegList[i]); in tryFoldSPUpdateIntoPushPop()
HDARMInstrInfo.td435 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.h91 ArrayRef<uint16_t> RegList; in CC_AArch64_Custom_Block() local
93 RegList = XRegList; in CC_AArch64_Custom_Block()
95 RegList = HRegList; in CC_AArch64_Custom_Block()
97 RegList = SRegList; in CC_AArch64_Custom_Block()
99 RegList = DRegList; in CC_AArch64_Custom_Block()
101 RegList = QRegList; in CC_AArch64_Custom_Block()
117 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); in CC_AArch64_Custom_Block()
129 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
/NextBSD/contrib/llvm/utils/TableGen/
HDCallingConvEmitter.cpp113 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
114 if (RegList->size() == 1) { in EmitAction()
116 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; in EmitAction()
121 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
123 O << getQualifiedName(RegList->getElementAsRecord(i)); in EmitAction()
134 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
136 if (!ShadowRegList->empty() && ShadowRegList->size() != RegList->size()) in EmitAction()
139 if (RegList->size() == 1) { in EmitAction()
141 O << getQualifiedName(RegList->getElementAsRecord(0)); in EmitAction()
151 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
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/NextBSD/contrib/llvm/lib/Target/ARM/MCTargetDesc/
HDARMELFStreamer.cpp73 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
137 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
139 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
145 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
147 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
149 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
369 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
435 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
642 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
644 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
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HDARMTargetStreamer.cpp53 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetCallingConv.td80 list<Register> RegList = regList;
87 list<Register> RegList = regList;
/NextBSD/contrib/llvm/lib/Target/Mips/AsmParser/
HDMipsAsmParser.cpp577 struct RegListOp RegList; member
960 int Size = RegList.List->size(); in isRegList16()
961 if (Size < 2 || Size > 5 || *RegList.List->begin() != Mips::S0 || in isRegList16()
962 RegList.List->back() != Mips::RA) in isRegList16()
965 int PrevReg = *RegList.List->begin(); in isRegList16()
967 int Reg = (*(RegList.List))[i]; in isRegList16()
984 if (Kind != k_RegList || RegList.List->size() != 2) in isMovePRegPair()
987 unsigned R0 = RegList.List->front(); in isMovePRegPair()
988 unsigned R1 = RegList.List->back(); in isMovePRegPair()
1046 return *(RegList.List); in getRegList()
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/NextBSD/contrib/llvm/include/llvm/MC/
HDMCStreamer.h111 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp286 static const MCPhysReg RegList[] = { in AnalyzeArguments() local
289 static const unsigned NbRegs = array_lengthof(RegList); in AnalyzeArguments()
331 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp56 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_f64() local
60 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_f64()
71 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_f64()
/NextBSD/contrib/llvm/lib/Target/ARM/AsmParser/
HDARMAsmParser.cpp1834 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListOperands() local
1836 I = RegList.begin(), E = RegList.end(); I != E; ++I) in addRegListOperands()
2942 const SmallVectorImpl<unsigned> &RegList = getRegList(); in print() local
2944 I = RegList.begin(), E = RegList.end(); I != E; ) { in print()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp224 static const MCPhysReg RegList[] = { in CC_Hexagon32() local
228 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Hexagon32()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMicroMipsInstrInfo.td484 let Name = "RegList";