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Searched refs:RegPressure (Results 1 – 14 of 14) sorted by relevance

/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDResourcePriorityQueue.cpp57 RegPressure.resize(NumRC); in ResourcePriorityQueue()
59 std::fill(RegPressure.begin(), RegPressure.end(), 0); in ResourcePriorityQueue()
377 if ((RegPressure[RC->getID()] + in regPressureDelta()
379 (RegPressure[RC->getID()] + in regPressureDelta()
491 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
502 if (RegPressure[RC->getID()] > in scheduledNode()
504 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
505 else RegPressure[RC->getID()] = 0; in scheduledNode()
HDScheduleDAGRRList.cpp1649 std::vector<unsigned> RegPressure; member in __anonc56399fd0211::RegReductionPQBase
1669 RegPressure.resize(NumRC); in RegReductionPQBase()
1671 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1695 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
1945 unsigned RP = RegPressure[Id]; in dumpRegPressure()
1972 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1991 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2023 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2038 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2085 RegPressure[RCId] += Cost; in scheduledNode()
[all …]
HDSelectionDAGISel.cpp300 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
/NextBSD/contrib/llvm/lib/CodeGen/
HDMachineLICM.cpp101 SmallVector<unsigned, 8> RegPressure; member in __anon5591c39d0111::MachineLICM
149 RegPressure.clear(); in releaseMemory()
360 RegPressure.resize(NumRPS); in runOnMachineFunction()
361 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
674 BackTrace.push_back(RegPressure); in EnterScope()
844 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
868 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second) in UpdateRegPressure()
869 RegPressure[Class] = 0; in UpdateRegPressure()
871 RegPressure[Class] += RPIdAndCost.second; in UpdateRegPressure()
/NextBSD/contrib/llvm/lib/Target/WebAssembly/
HDWebAssemblyISelLowering.cpp42 setSchedulingPreference(Sched::RegPressure); in WebAssemblyTargetLowering()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineScheduler.h364 IntervalPressure RegPressure; variable
385 ShouldTrackPressure(false), RPTracker(RegPressure), in ScheduleDAGMILive()
405 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
HDResourcePriorityQueue.h53 std::vector<unsigned> RegPressure; variable
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetLowering.h70 RegPressure, // Scheduling for lowest register pressure. enumerator
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp956 setSchedulingPreference(Sched::RegPressure); in ARMTargetLowering()
1214 return Sched::RegPressure; in getSchedulingPreference()
1225 return Sched::RegPressure; in getSchedulingPreference()
1233 return Sched::RegPressure; in getSchedulingPreference()
1238 return Sched::RegPressure; in getSchedulingPreference()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp244 setSchedulingPreference(Sched::RegPressure); in SITargetLowering()
HDAMDGPUISelLowering.cpp421 setSchedulingPreference(Sched::RegPressure); in AMDGPUTargetLowering()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp129 setSchedulingPreference(Sched::RegPressure); in NVPTXTargetLowering()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp126 setSchedulingPreference(Sched::RegPressure); in SystemZTargetLowering()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp97 setSchedulingPreference(Sched::RegPressure); in X86TargetLowering()