Searched refs:SCIdx (Results 1 – 5 of 5) sorted by relevance
516 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); in collectSchedClasses() local517 InstrClassMap[Inst->TheDef] = SCIdx; in collectSchedClasses()534 unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef); in collectSchedClasses() local535 if (!SCIdx) { in collectSchedClasses()539 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()559 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()685 unsigned SCIdx = Pos->second; in createInstRWClass() local688 if (ClassInstrs[CIdx].first == SCIdx) in createInstRWClass()693 ClassInstrs[CIdx].first = SCIdx; in createInstRWClass()726 unsigned SCIdx = SchedClasses.size(); in createInstRWClass() local[all …]
1143 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) { in EmitSchedClassTables() local1144 MCSchedClassDesc &MCDesc = SCTab[SCIdx]; in EmitSchedClassTables()1145 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()1157 if (SCIdx + 1 < SCEnd) in EmitSchedClassTables()1159 OS << " // #" << SCIdx << '\n'; in EmitSchedClassTables()
406 void inferFromInstRWs(unsigned SCIdx);
81 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock() local83 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldAddSTPToBlock()
243 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency() local244 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx); in computeInstrLatency()