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Searched refs:SETGE (Results 1 – 25 of 35) sorted by relevance

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/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h826 SETGE, // 1 X 0 1 1 True if greater than or equal enumerator
838 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/NextBSD/contrib/llvm/lib/CodeGen/
HDAnalysis.cpp190 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
204 case ICmpInst::ICMP_SGE: return ISD::SETGE; in getICmpCondCode()
HDTargetLoweringBase.cpp728 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs()
729 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs()
730 CCs[RTLIB::OGE_F128] = ISD::SETGE; in InitCmpLibcallCCs()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonSelectCCInfo.td63 IntRegs:$fval, SETGE)),
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrCMovSetCC.td109 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal
HDX86IntrinsicsInfo.h1010 X86_INTRINSIC_DATA(sse2_comige_sd, COMI, X86ISD::COMI, ISD::SETGE),
1050 X86_INTRINSIC_DATA(sse2_ucomige_sd, COMI, X86ISD::UCOMI, ISD::SETGE),
1085 X86_INTRINSIC_DATA(sse_comige_ss, COMI, X86ISD::COMI, ISD::SETGE),
1096 X86_INTRINSIC_DATA(sse_ucomige_ss, COMI, X86ISD::UCOMI, ISD::SETGE),
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDTargetLowering.cpp141 case ISD::SETGE: in softenSetCCOperands()
1454 case ISD::SETGE: in SimplifySetCC()
1618 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1622 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
1650 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
2053 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
HDSelectionDAGDumper.cpp332 case ISD::SETGE: return "setge"; in getOperationName()
HDLegalizeIntegerTypes.cpp946 case ISD::SETGE: in PromoteSetCCOperands()
2131 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO()
2132 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO()
2137 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO()
2689 case ISD::SETGE: in IntegerExpandSetCCOperands()
2722 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || in IntegerExpandSetCCOperands()
HDLegalizeDAG.cpp1747 case ISD::SETGE: in LegalizeSetCCCondCode()
3708 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); in ExpandNode()
3709 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); in ExpandNode()
3714 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); in ExpandNode()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUInstructions.td86 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
126 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
HDR600Instructions.td706 0xA, "SETGE",
801 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
1667 def : CND_INT_f32 <CNDGE_INT, SETGE>;
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrQPX.td1027 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETGE),
1074 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETGE),
1127 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETGE)),
1148 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETGE)),
1169 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETGE)),
HDPPCInstrInfo.td2895 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3003 defm : ExtSetCCPat<SETGE,
3035 defm : ExtSetCCPat<SETGE,
3090 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3118 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3158 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3186 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3213 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3244 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3280 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
[all …]
HDPPCISelDAGToDAG.cpp2054 case ISD::SETGE: return PPC::PRED_GE; in getPredicateForSetCC()
2078 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE in getCRIdxForSetCC()
2106 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break; in getVCmpInst()
2138 case ISD::SETGE: in getVCmpInst()
2152 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break; in getVCmpInst()
HDPPCInstrVSX.td970 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
991 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
1090 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp591 case ISD::SETGE: in EmitInstrWithCustomInserter()
HDBPFInstrInfo.td73 [{return (N->getZExtValue() == ISD::SETGE);}]>;
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp1252 case ISD::SETGE: return ARMCC::GE; in IntCCToARMCC()
1272 case ISD::SETGE: in FPCCToARMCC()
3215 case ISD::SETGE: in getARMCmp()
3231 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getARMCmp()
3612 case ISD::SETGE: in LowerSELECT_CC()
3651 case ISD::SETGE: in LowerSELECT_CC()
4243 ISD::SETGE, ARMcc, DAG, dl); in LowerShiftRightParts()
4277 ISD::SETGE, ARMcc, DAG, dl); in LowerShiftLeftParts()
4606 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
4639 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsDSPInstrInfo.td1364 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1377 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
HDMipsSEISelLowering.cpp287 setCondCodeAction(ISD::SETGE, Ty, Expand); in addMSAIntType()
327 setCondCodeAction(ISD::SETGE, Ty, Expand); in addMSAFloatType()
962 case ISD::SETGE: return IsV216; in isLegalDSPCondCode()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td563 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
926 (setcc node:$lhs, node:$rhs, SETGE)>;
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp1015 case ISD::SETGE: in changeIntCCToAArch64CC()
1048 case ISD::SETGE: in changeFPCCToAArch64CC()
1187 case ISD::SETGE: in getAArch64Cmp()
1213 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getAArch64Cmp()
4125 ISD::SETGE, dl, DAG); in LowerShiftRightParts()
4173 ISD::SETGE, dl, DAG); in LowerShiftLeftParts()
8918 case ISD::SETGE: in performSelectCCCombine()
8919 IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE); in performSelectCCCombine()
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp865 case ISD::SETGE: in EmitCMP()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1334 case ISD::SETGE: return SPCC::ICC_GE; in IntCondCCodeToICC()
1357 case ISD::SETGE: in FPCondCCodeToFCC()

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