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Searched refs:SETUGT (Results 1 – 25 of 33) sorted by relevance

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/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h816 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
844 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/NextBSD/contrib/llvm/lib/CodeGen/
HDAnalysis.cpp173 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
189 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
209 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDTargetLowering.cpp178 case ISD::SETUGT: in softenSetCCOperands()
1314 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1447 case ISD::SETUGT: in SimplifySetCC()
1470 case ISD::SETUGT: in SimplifySetCC()
1622 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
1652 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
1658 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
1670 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
1679 if (Cond == ISD::SETUGT && in SimplifySetCC()
1749 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
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HDSelectionDAGDumper.cpp324 case ISD::SETUGT: return "setugt"; in getOperationName()
HDLegalizeIntegerTypes.cpp937 case ISD::SETUGT: in PromoteSetCCOperands()
2387 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2686 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
2726 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
HDLegalizeDAG.cpp1731 case ISD::SETUGT: in LegalizeSetCCCondCode()
3321 Tmp1, Tmp2, ISD::SETUGT); in ExpandNode()
3337 case ISD::UMAX: Pred = ISD::SETUGT; break; in ExpandNode()
3733 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT; in ExpandNode()
HDSelectionDAG.cpp308 case ISD::SETUGT: in isSignedOp()
358 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE in getSetCCAndOperation()
1928 case ISD::SETUGT: return getConstant(C1.ugt(C2), dl, VT); in FoldSetCC()
1977 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonSelectCCInfo.td30 IntRegs:$fval, SETUGT)),
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrQPX.td1007 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGT),
1054 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGT),
1133 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGT)),
1154 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGT)),
1175 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGT)),
HDPPCISelDAGToDAG.cpp2059 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
2091 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
2111 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
2155 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; in getVCmpInst()
2163 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break; in getVCmpInst()
2189 case ISD::SETUGT: in getVCmpInst()
HDPPCInstrInfo.td2913 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2920 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3064 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3109 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3132 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3177 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3289 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3313 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3334 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3355 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
[all …]
HDPPCInstrVSX.td976 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)),
997 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
1096 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
290 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
326 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
965 case ISD::SETUGT: in isLegalDSPCondCode()
HDMipsDSPInstrInfo.td1371 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1384 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp585 case ISD::SETUGT: in EmitInstrWithCustomInserter()
HDBPFInstrInfo.td77 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp1255 case ISD::SETUGT: return ARMCC::HI; in IntCCToARMCC()
1280 case ISD::SETUGT: CondCode = ARMCC::HI; break; in FPCCToARMCC()
3224 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getARMCmp()
3236 case ISD::SETUGT: in getARMCmp()
3442 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT || in checkVSELConstraints()
3461 CC == ISD::SETUGT) { in checkVSELConstraints()
3580 case ISD::SETUGT: in LowerSELECT_CC()
3604 case ISD::SETUGT: in LowerSELECT_CC()
3646 case ISD::SETUGT: in LowerSELECT_CC()
4609 case ISD::SETUGT: Swap = true; // Fallthrough in LowerVSETCC()
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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUInstructions.td109 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
HDAMDGPUISelLowering.cpp1147 case ISD::SETUGT: { in CombineFMinMaxLegacy()
1200 case ISD::SETUGT: { in CombineIMinMax()
HDR600Instructions.td811 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td560 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
912 (setcc node:$lhs, node:$rhs, SETUGT)>;
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp850 case ISD::SETUGT: in EmitCMP()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp1021 case ISD::SETUGT: in changeIntCCToAArch64CC()
1072 case ISD::SETUGT: in changeFPCCToAArch64CC()
1116 case ISD::SETUGT: in changeVectorFPCCToAArch64CC()
1202 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getAArch64Cmp()
1219 case ISD::SETUGT: in getAArch64Cmp()
8912 case ISD::SETUGT: in performSelectCCCombine()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1337 case ISD::SETUGT: return SPCC::ICC_GU; in IntCondCCodeToICC()
1361 case ISD::SETUGT: return SPCC::FCC_UG; in FPCondCCodeToFCC()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp3845 case ISD::SETUGT: return X86::COND_A; in TranslateX86CC()
3864 case ISD::SETUGT: in TranslateX86CC()
3886 case ISD::SETUGT: // flipped in TranslateX86CC()
13378 case ISD::SETUGT: SSECC = 6; break; in translateX86FSETCC()
13443 case ISD::SETUGT: in LowerBoolVSETCC_AVX512()
13483 case ISD::SETUGT: SSECC = 6; Unsigned = true; break; in LowerIntVSETCC_AVX512()
13648 case ISD::SETUGT: Opc = X86ISD::PCMPGT; in LowerVSETCC()
22096 case ISD::SETUGT: in matchIntegerMINMAX()
22114 case ISD::SETUGT: in matchIntegerMINMAX()
22241 case ISD::SETUGT: in PerformSELECTCombine()
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