| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 820 SETUNE, // 1 1 1 0 True if unordered or not equal enumerator
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | Analysis.cpp | 177 case FCmpInst::FCMP_UNE: return ISD::SETUNE; in getFCmpCondCode()
186 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUInstructions.td | 108 def COND_UNE : PatLeaf <(cond), [{return N->get() == ISD::SETUNE;}]>;
118 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
141 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
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| HD | SIISelLowering.cpp | 1620 if (RCC == ISD::SETUNE) { in performAndCombine()
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| HD | R600ISelLowering.cpp | 1204 case ISD::SETUNE: in LowerSELECT_CC()
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| HD | AMDGPUISelLowering.cpp | 1110 case ISD::SETUNE: in CombineFMinMaxLegacy()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 328 case ISD::SETUNE: return "setune"; in getOperationName()
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| HD | TargetLowering.cpp | 137 case ISD::SETUNE: in softenSetCCOperands()
1823 if (Cond == ISD::SETUNE && in SimplifySetCC()
1836 if (Cond == ISD::SETUNE && in SimplifySetCC()
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| HD | LegalizeDAG.cpp | 1719 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT) in LegalizeSetCCCondCode()
1722 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break; in LegalizeSetCCCondCode()
1730 case ISD::SETUNE: in LegalizeSetCCCondCode()
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| HD | SelectionDAG.cpp | 331 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT in getSetCCOrOperation()
1913 case ISD::SETUNE: in FoldSetCC()
1974 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, dl, VT); in FoldSetCC()
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| HD | LegalizeFloatTypes.cpp | 1432 LHSHi, RHSHi, ISD::SETUNE); in FloatExpandSetCCOperands()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelDAGToDAG.cpp | 2045 case ISD::SETUNE: in getPredicateForSetCC()
2081 case ISD::SETUNE: in getCRIdxForSetCC()
2117 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break; in getVCmpInst()
2161 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break; in getVCmpInst()
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| HD | PPCInstrQPX.td | 1019 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUNE),
1066 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUNE),
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| HD | PPCInstrInfo.td | 3219 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3250 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 561 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
920 (setcc node:$lhs, node:$rhs, SETUNE)>;
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 1287 case ISD::SETUNE: CondCode = ARMCC::NE; break; in FPCCToARMCC()
3476 if (CC == ISD::SETUNE) { in checkVSELConstraints()
3785 else if (CC == ISD::SETUNE) in OptimizeVFPBrcond()
3849 CC == ISD::SETNE || CC == ISD::SETUNE)) { in LowerBR_CC()
4595 case ISD::SETUNE: in LowerVSETCC()
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| /NextBSD/contrib/llvm/lib/Target/NVPTX/ |
| HD | NVPTXVector.td | 978 (setcc node:$lhs, node:$rhs, SETUNE)>;
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 1573 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); in HexagonTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsMSAInstrInfo.td | 206 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
207 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
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| HD | MipsSEISelLowering.cpp | 1832 Op->getOperand(2), ISD::SETUNE); in lowerINTRINSIC_WO_CHAIN()
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| HD | MipsISelLowering.cpp | 514 case ISD::SETUNE: return Mips::FCOND_UNE; in condCodeToFCC()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcISelLowering.cpp | 1350 case ISD::SETUNE: return SPCC::FCC_NE; in FPCondCCodeToFCC()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); in X86TargetLowering()
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); in X86TargetLowering()
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); in X86TargetLowering()
3897 case ISD::SETUNE: return X86::COND_INVALID; in TranslateX86CC()
13373 case ISD::SETUNE: in translateX86FSETCC()
14806 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { in LowerBRCOND()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 1087 case ISD::SETUNE: in changeFPCCToAArch64CC()
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