Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 – 8 of 8) sorted by relevance
| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 423 SIGN_EXTEND_VECTOR_INREG, enumerator
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeVectorOps.cpp | 323 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
695 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
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| HD | SelectionDAGDumper.cpp | 235 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
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| HD | DAGCombiner.cpp | 1368 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N); in visit()
5597 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
5633 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
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| HD | SelectionDAG.cpp | 1087 return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op); in getSignExtendVectorInReg()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 838 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /NextBSD/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZISelLowering.cpp | 323 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4372 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
4568 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); in X86TargetLowering()
1015 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); in X86TargetLowering()
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); in X86TargetLowering()
18564 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
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