Searched refs:ShiftTy (Results 1 – 6 of 6) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/ARM/AsmParser/ |
| HD | ARMAsmParser.cpp | 504 ARM_AM::ShiftOpc ShiftTy; member
514 ARM_AM::ShiftOpc ShiftTy; member
521 ARM_AM::ShiftOpc ShiftTy; member
1122 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1243 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1812 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
1823 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands()
2396 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands()
2626 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
2639 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | TargetLowering.cpp | 1702 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1711 ShiftTy))); in SimplifySetCC()
1720 ShiftTy))); in SimplifySetCC()
1737 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1743 ShiftTy)); in SimplifySetCC()
1769 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1774 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
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| HD | LegalizeIntegerTypes.cpp | 2213 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
2214 assert(ShiftTy.getScalarType().getSizeInBits() >= in ExpandIntRes_Shift()
2217 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2218 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
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| HD | SelectionDAGBuilder.cpp | 2179 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
2183 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
2184 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift()
2190 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
2197 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift()
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsSEISelLowering.cpp | 797 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
812 DAG.getConstant(Log2_64(C), DL, ShiftTy)); in genConstMult()
822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMFastISel.cpp | 163 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2758 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2801 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2804 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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