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Searched refs:Subtarget (Results 1 – 25 of 146) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsRegisterInfo.cpp86 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
87 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
90 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
93 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
96 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
99 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
108 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
109 if (Subtarget.isSingleFloat()) in getCallPreservedMask()
112 if (Subtarget.isABI_N64()) in getCallPreservedMask()
115 if (Subtarget.isABI_N32()) in getCallPreservedMask()
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HDMipsSEInstrInfo.cpp84 bool isMicroMips = Subtarget.inMicroMipsMode(); in copyPhysReg()
265 bool isMicroMips = Subtarget.inMicroMipsMode(); in expandPostRAPseudo()
362 MipsABIInfo ABI = Subtarget.getABI(); in adjustStackPtr()
385 const MipsSubtarget &STI = Subtarget; in loadImmediate()
434 if (Subtarget.isGP64bit()) in expandRetRA()
526 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); in expandExtractElementF64()
530 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); in expandExtractElementF64()
532 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { in expandExtractElementF64()
577 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); in expandBuildPairF64()
581 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); in expandBuildPairF64()
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HDMipsSEFrameLowering.cpp74 const MipsSubtarget &Subtarget; member in __anon54efea600111::ExpandPseudo
82 Subtarget(static_cast<const MipsSubtarget &>(MF.getSubtarget())), in ExpandPseudo()
83 TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())), in ExpandPseudo()
84 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
282 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || in expandBuildPairF64()
283 (FP64 && !Subtarget.useOddSPReg())) { in expandBuildPairF64()
291 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() || in expandBuildPairF64()
292 !Subtarget.isFP64bit()); in expandBuildPairF64()
301 if (!Subtarget.isLittle()) in expandBuildPairF64()
335 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || in expandExtractElementF64()
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HDMipsSEISelLowering.cpp44 if (Subtarget.isGP64bit()) in MipsSETargetLowering()
47 if (Subtarget.hasDSP() || Subtarget.hasMSA()) { in MipsSETargetLowering()
59 if (Subtarget.hasDSP()) { in MipsSETargetLowering()
83 if (Subtarget.hasDSPR2()) in MipsSETargetLowering()
86 if (Subtarget.hasMSA()) { in MipsSETargetLowering()
102 if (!Subtarget.useSoftFloat()) { in MipsSETargetLowering()
106 if (!Subtarget.isSingleFloat()) { in MipsSETargetLowering()
107 if (Subtarget.isFP64bit()) in MipsSETargetLowering()
119 if (Subtarget.hasCnMips()) in MipsSETargetLowering()
121 else if (Subtarget.isGP64bit()) in MipsSETargetLowering()
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HDMipsISelLowering.cpp226 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { in MipsTargetLowering()
233 if (Subtarget.hasMips32r6()) in MipsTargetLowering()
288 if (Subtarget.isGP64bit()) { in MipsTargetLowering()
303 if (!Subtarget.isGP64bit()) { in MipsTargetLowering()
310 if (Subtarget.isGP64bit()) in MipsTargetLowering()
334 if (Subtarget.hasCnMips()) { in MipsTargetLowering()
352 if (!Subtarget.hasMips32r2()) in MipsTargetLowering()
355 if (!Subtarget.hasMips64r2()) in MipsTargetLowering()
400 if (!Subtarget.hasMips32r2()) { in MipsTargetLowering()
406 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) in MipsTargetLowering()
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HDMipsAsmPrinter.cpp61 Subtarget = &MF.getSubtarget<MipsSubtarget>(); in runOnMachineFunction()
68 if (Subtarget->inMips16Mode()) in runOnMachineFunction()
82 if (Subtarget->isTargetNaCl()) in runOnMachineFunction()
103 if (Subtarget->hasMips64r6()) { in emitPseudoIndirectBranch()
107 } else if (Subtarget->hasMips32r6()) { in emitPseudoIndirectBranch()
111 } else if (Subtarget->inMicroMipsMode()) in emitPseudoIndirectBranch()
122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch()
200 if (I->isPseudo() && !Subtarget->inMips16Mode() in EmitInstruction()
326 if (Subtarget->isTargetNaCl()) in EmitFunctionEntryLabel()
329 if (Subtarget->inMicroMipsMode()) in EmitFunctionEntryLabel()
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HDMips16ISelDAGToDAG.cpp40 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); in runOnMachineFunction()
41 if (!Subtarget->inMips16Mode()) in runOnMachineFunction()
75 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in initGlobalBaseReg()
105 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in initMips16SPAliasReg()
137 AliasReg = Subtarget->getFrameLowering()->hasFP(*MF) in getMips16SPRefReg()
149 AliasReg = Subtarget->getFrameLowering()->hasFP(*MF) in getMips16SPRefReg()
232 if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2()) in selectAddr16()
234 if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2()) in selectAddr16()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCRegisterInfo.cpp103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
105 if (Subtarget.hasVSX()) in getCalleeSavedRegs()
107 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
112 if (Subtarget.isDarwinABI()) in getCalleeSavedRegs()
114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList in getCalleeSavedRegs()
116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList in getCalleeSavedRegs()
123 ? (Subtarget.hasAltivec() in getCalleeSavedRegs()
127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList in getCalleeSavedRegs()
134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); in getCallPreservedMask() local
136 if (Subtarget.hasVSX()) in getCallPreservedMask()
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HDPPCFrameLowering.cpp87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
90 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
96 if (Subtarget.isDarwinABI()) { in getCalleeSavedSpillSlots()
98 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
108 if (!Subtarget.isSVR4ABI()) { in getCalleeSavedSpillSlots()
238 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
438 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); in determineFrameLayout()
448 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- in determineFrameLayout()
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HDPPCISelLowering.cpp63 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
70 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
102 if (Subtarget.useCRBits()) { in PPCTargetLowering()
105 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
179 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && in PPCTargetLowering()
181 Subtarget.hasFRE())) in PPCTargetLowering()
184 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() && in PPCTargetLowering()
186 Subtarget.hasFRES())) in PPCTargetLowering()
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HDPPCAsmPrinter.cpp71 const PPCSubtarget *Subtarget; member in __anonda0e7a4c0111::PPCAsmPrinter
103 Subtarget = &MF.getSubtarget<PPCSubtarget>(); in runOnMachineFunction()
174 if (!Subtarget->isDarwin()) in printOperand()
290 if (!Subtarget->isDarwin()) in PrintAsmMemoryOperand()
398 int TOCSaveOffset = Subtarget->isELFv2ABI() ? 24 : 40; in LowerPATCHPOINT()
408 if (!Subtarget->isELFv2ABI()) { in LowerPATCHPOINT()
469 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) || in EmitTlsCall()
470 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) && in EmitTlsCall()
473 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) || in EmitTlsCall()
474 (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) && in EmitTlsCall()
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/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcRegisterInfo.cpp57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
68 if (!Subtarget.is64Bit()) in getReservedRegs()
79 if (!Subtarget.isV9()) { in getReservedRegs()
92 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
93 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
164 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
167 Subtarget.getStackPointerBias(); in eliminateFrameIndex()
174 Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ; in eliminateFrameIndex()
177 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
179 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
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HDDelaySlotFiller.cpp45 const SparcSubtarget *Subtarget; member
57 Subtarget = &F.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
110 Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>(); in runOnMachineBasicBlock()
111 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in runOnMachineBasicBlock()
125 if (!Subtarget->isV9() && in runOnMachineBasicBlock()
188 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); in findDelayInstr()
330 for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true); in IsRegInSet()
483 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in tryCombineRestoreWithPrevInst()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp76 : TargetLowering(TM), Subtarget(&STI) { in X86TargetLowering()
77 X86ScalarSSEf64 = Subtarget->hasSSE2(); in X86TargetLowering()
78 X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86TargetLowering()
92 if (Subtarget->isAtom()) in X86TargetLowering()
94 else if (Subtarget->is64Bit()) in X86TargetLowering()
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo(); in X86TargetLowering()
103 if (Subtarget->hasSlowDivide32()) in X86TargetLowering()
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit()) in X86TargetLowering()
109 if (Subtarget->isTargetKnownWindowsMSVC()) { in X86TargetLowering()
130 if (Subtarget->isTargetDarwin()) { in X86TargetLowering()
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HDX86SelectionDAGInfo.cpp55 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
73 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) { in EmitTargetCodeForMemset()
78 V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) { in EmitTargetCodeForMemset()
128 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned in EmitTargetCodeForMemset()
157 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
160 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemset()
208 const X86Subtarget &Subtarget = in EmitTargetCodeForMemcpy() local
213 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
244 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in EmitTargetCodeForMemcpy()
252 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : in EmitTargetCodeForMemcpy()
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HDX86FastISel.cpp51 const X86Subtarget *Subtarget; member in __anond7f8f08b0111::X86FastISel
64 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>(); in X86FastISel()
65 X86ScalarSSEf64 = Subtarget->hasSSE2(); in X86FastISel()
66 X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86FastISel()
136 return Subtarget->getInstrInfo(); in getInstrInfo()
375 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
384 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; in X86FastEmitLoad()
396 Opc = Subtarget->hasAVX() ? X86::VMOVAPSrm : X86::MOVAPSrm; in X86FastEmitLoad()
398 Opc = Subtarget->hasAVX() ? X86::VMOVUPSrm : X86::MOVUPSrm; in X86FastEmitLoad()
403 Opc = Subtarget->hasAVX() ? X86::VMOVAPDrm : X86::MOVAPDrm; in X86FastEmitLoad()
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/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp159 : TargetLowering(TM), Subtarget(&STI) { in ARMTargetLowering()
160 RegInfo = Subtarget->getRegisterInfo(); in ARMTargetLowering()
161 Itins = Subtarget->getInstrItineraryData(); in ARMTargetLowering()
165 if (Subtarget->isTargetMachO()) { in ARMTargetLowering()
167 if (Subtarget->isThumb() && Subtarget->hasVFP2() && in ARMTargetLowering()
168 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) { in ARMTargetLowering()
248 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() && in ARMTargetLowering()
249 !Subtarget->isTargetWindows()) { in ARMTargetLowering()
353 if (Subtarget->isTargetWindows()) { in ARMTargetLowering()
376 if (Subtarget->getTargetTriple().isiOS() && in ARMTargetLowering()
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HDARMBaseInstrInfo.cpp97 Subtarget(STI) { in ARMBaseInstrInfo()
122 if (Subtarget.isThumb2() || Subtarget.hasVFP2()) in CreateTargetPostRAHazardRecognizer()
662 const ARMSubtarget &Subtarget) const { in copyFromCPSR()
663 unsigned Opc = Subtarget.isThumb() in copyFromCPSR()
664 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
672 if (Subtarget.isMClass()) in copyFromCPSR()
683 const ARMSubtarget &Subtarget) const { in copyToCPSR()
684 unsigned Opc = Subtarget.isThumb() in copyToCPSR()
685 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
690 if (Subtarget.isMClass()) in copyToCPSR()
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HDARMFastISel.cpp79 const ARMSubtarget *Subtarget; member in __anonced15ebf0111::ARMFastISel
94 Subtarget( in ARMFastISel()
97 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()), in ARMFastISel()
98 TLI(*Subtarget->getTargetLowering()) { in ARMFastISel()
489 if (!Subtarget->hasVFP2()) return false; in ARMMaterializeFP()
517 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { in ARMMaterializeInt()
529 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { in ARMMaterializeInt()
546 if (Subtarget->useMovt(*FuncInfo.MF)) in ARMMaterializeInt()
584 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM); in ARMMaterializeGV()
592 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0; in ARMMaterializeGV()
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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonAsmPrinter.cpp67 : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr) {} in HexagonAsmPrinter()
205 HexagonMCInstrInfo::tryCompound(*Subtarget->getInstrInfo(), in EmitInstruction()
211 *Subtarget->getInstrInfo(), MCB); in EmitInstruction()
212 HexagonMCShuffle(*Subtarget->getInstrInfo(), *Subtarget, in EmitInstruction()
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFTargetMachine.h23 BPFSubtarget Subtarget; variable
30 const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()
32 return &Subtarget; in getSubtargetImpl()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreTargetMachine.h24 XCoreSubtarget Subtarget; variable
32 const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()
34 return &Subtarget; in getSubtargetImpl()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZTargetMachine.h27 SystemZSubtarget Subtarget; variable
36 const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()
38 return &Subtarget; in getSubtargetImpl()
/NextBSD/contrib/llvm/lib/Target/WebAssembly/
HDWebAssemblyISelDAGToDAG.cpp35 const WebAssemblySubtarget *Subtarget; member in __anonb236ad880111::WebAssemblyDAGToDAGISel
42 : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr), ForCodeSize(false) { in WebAssemblyDAGToDAGISel()
53 Subtarget = &MF.getSubtarget<WebAssemblySubtarget>(); in runOnMachineFunction()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUTargetMachine.h36 AMDGPUSubtarget Subtarget; variable
45 const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()
47 return &Subtarget; in getSubtargetImpl()

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