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Searched refs:TRUNCATE (Results 1 – 25 of 71) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp511 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, in getCastInstrCost()
512 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, in getCastInstrCost()
513 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, in getCastInstrCost()
514 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, in getCastInstrCost()
515 { ISD::TRUNCATE, MVT::v16i32, MVT::v8i64, 4 }, in getCastInstrCost()
569 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, in getCastInstrCost()
570 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, in getCastInstrCost()
571 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, in getCastInstrCost()
572 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, in getCastInstrCost()
573 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, in getCastInstrCost()
[all …]
HDX86ISelLowering.cpp729 setOperationAction(ISD::TRUNCATE, VT, Expand); in X86TargetLowering()
1120 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom); in X86TargetLowering()
1121 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom); in X86TargetLowering()
1122 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom); in X86TargetLowering()
1351 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in X86TargetLowering()
1352 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom); in X86TargetLowering()
1353 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom); in X86TargetLowering()
1355 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom); in X86TargetLowering()
1356 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom); in X86TargetLowering()
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom); in X86TargetLowering()
[all …]
/NextBSD/crypto/openssl/crypto/bio/
HDb_dump.c67 #define TRUNCATE macro
88 #ifdef TRUNCATE in BIO_dump_indent_cb()
143 #ifdef TRUNCATE in BIO_dump_indent_cb()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp85 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
86 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
101 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
102 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
232 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 }, in getCastInstrCost()
233 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 }, in getCastInstrCost()
234 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, in getCastInstrCost()
235 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 } in getCastInstrCost()
HDARMSelectionDAGInfo.cpp95 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); in EmitSpecializedLibcall()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDTargetLowering.cpp356 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
358 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
982 case ISD::TRUNCATE: { in SimplifyDemandedBits()
1025 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, in SimplifyDemandedBits()
1303 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
1372 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); in SimplifySetCC()
1528 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); in SimplifySetCC()
1571 if (Op0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
1588 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
1708 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
[all …]
HDDAGCombiner.cpp913 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); in ReplaceLoadWithPromotedLoad()
1048 return DAG.getNode(ISD::TRUNCATE, dl, VT, in PromoteIntBinOp()
1095 return DAG.getNode(ISD::TRUNCATE, dl, VT, in PromoteIntShiftOp()
1161 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); in PromoteLoad()
1369 case ISD::TRUNCATE: return visitTRUNCATE(N); in visit()
2440 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); in visitMULHS()
2476 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); in visitMULHU()
2555 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); in visitSMUL_LOHI()
2557 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); in visitSMUL_LOHI()
2586 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); in visitUMUL_LOHI()
[all …]
HDLegalizeIntegerTypes.cpp83 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; in PromoteIntegerResult()
603 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); in PromoteIntRes_SETCC()
683 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1); in PromoteIntRes_TRUNCATE()
684 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2); in PromoteIntRes_TRUNCATE()
690 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); in PromoteIntRes_TRUNCATE()
878 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; in PromoteIntegerOperand()
1206 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op); in PromoteIntOp_TRUNCATE()
1277 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; in ExpandIntegerResult()
2362 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); in ExpandIntRes_TRUNCATE()
2367 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); in ExpandIntRes_TRUNCATE()
[all …]
HDLegalizeVectorTypes.cpp97 case ISD::TRUNCATE: in ScalarizeVectorResult()
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_BUILD_VECTOR()
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op); in ScalarizeVecRes_INSERT_VECTOR_ELT()
275 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_SCALAR_TO_VECTOR()
432 case ISD::TRUNCATE: in ScalarizeVectorOperand()
644 case ISD::TRUNCATE: in SplitVectorResult()
1356 case ISD::TRUNCATE: in SplitVectorOperand()
1854 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec); in SplitVecOp_TruncateHelper()
1986 case ISD::TRUNCATE: in WidenVectorResult()
2847 case ISD::TRUNCATE: in WidenVectorOperand()
HDSelectionDAG.cpp1034 getNode(ISD::TRUNCATE, DL, VT, Op); in getAnyExtOrTrunc()
1040 getNode(ISD::TRUNCATE, DL, VT, Op); in getSExtOrTrunc()
1046 getNode(ISD::TRUNCATE, DL, VT, Op); in getZExtOrTrunc()
1052 return getNode(ISD::TRUNCATE, SL, VT, Op); in getBoolExtOrTrunc()
1855 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in getShiftAmountOperand()
2307 case ISD::TRUNCATE: { in computeKnownBits()
2667 case ISD::TRUNCATE: in ComputeNumSignBits()
2834 case ISD::TRUNCATE: in getNode()
2948 case ISD::TRUNCATE: in getNode()
2978 OpN = getNode(ISD::TRUNCATE, DL, InSVT, OpN); in getNode()
[all …]
HDLegalizeDAG.cpp602 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in PerformInsertVectorEltInMemory()
871 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value); in LegalizeStoreOps()
2567 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); in ExpandLegalINT_TO_FP()
2573 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); in ExpandLegalINT_TO_FP()
2713 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); in PromoteLegalFP_TO_INT()
3274 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); in ExpandNode()
3277 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), in ExpandNode()
4137 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); in PromoteNode()
4172 TruncOp = ISD::TRUNCATE; in PromoteNode()
4203 TruncOp = ISD::TRUNCATE; in PromoteNode()
[all …]
HDLegalizeTypes.cpp1119 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op); in SplitInteger()
1123 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); in SplitInteger()
HDLegalizeVectorOps.cpp293 case ISD::TRUNCATE: in LegalizeOp()
481 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted); in PromoteFP_TO_INT()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h389 TRUNCATE, enumerator
/NextBSD/contrib/binutils/ld/
HDldlex.l330 <MRI>"TRUNCATE" { RTOKEN(TRUNCATE); }
347 <MRI>"truncate" { RTOKEN(TRUNCATE); }
HDldgram.y148 %token FORMAT PUBLIC DEFSYMEND BASE ALIAS TRUNCATE REL
245 | TRUNCATE INT
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp1512 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0); in LowerCall()
1540 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0); in LowerCall()
1542 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1); in LowerCall()
1591 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt); in LowerCall()
1638 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0); in LowerCall()
1847 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select); in LowerSelect()
1874 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD); in LowerLOADi1()
4194 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS); in TryMULWIDECombine()
4196 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS); in TryMULWIDECombine()
4344 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
[all …]
/NextBSD/contrib/gcc/
HDsimplify-rtx.c605 return simplify_gen_unary (TRUNCATE, mode, temp, inner); in simplify_unary_operation_1()
615 return simplify_gen_unary (TRUNCATE, mode, temp, inner); in simplify_unary_operation_1()
620 case TRUNCATE: in simplify_unary_operation_1()
646 && GET_CODE (SUBREG_REG (op)) == TRUNCATE in simplify_unary_operation_1()
648 return simplify_gen_unary (TRUNCATE, mode, XEXP (SUBREG_REG (op), 0), in simplify_unary_operation_1()
810 if (GET_CODE (op) == TRUNCATE in simplify_unary_operation_1()
1050 case TRUNCATE: in simplify_const_unary_operation()
1196 case TRUNCATE: in simplify_const_unary_operation()
4581 if (GET_CODE (op) == TRUNCATE in simplify_subreg()
4584 return simplify_gen_unary (TRUNCATE, outermode, XEXP (op, 0), in simplify_subreg()
HDregrename.c546 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE in scan_rtx_address()
553 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE in scan_rtx_address()
1470 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE in replace_oldest_value_addr()
1477 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE in replace_oldest_value_addr()
HDsched-vis.c294 case TRUNCATE: in print_exp()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in PPCTargetLowering()
845 setTargetDAGCombine(ISD::TRUNCATE); in PPCTargetLowering()
2255 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); in LowerSETCC()
2877 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue); in LowerFormalArguments_32SVR4()
3011 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal); in extendArgForPPC64()
3297 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); in LowerFormalArguments_64SVR4()
3642 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal); in LowerFormalArguments_Darwin()
4313 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); in LowerCallResult()
4318 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); in LowerCallResult()
4323 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); in LowerCallResult()
[all …]
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp818 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1792 if (C.Op0.getOpcode() == ISD::TRUNCATE && in adjustICmpTruncate()
2134 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi); in lowerMUL_LOHI32()
2135 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul); in lowerMUL_LOHI32()
2680 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift); in lowerBITCAST()
2838 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1); in lowerSDIVREM()
2921 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp); in lowerOR()
2981 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op); in lowerCTPOP()
3058 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in lowerATOMIC_LOAD_OP()
3162 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in lowerATOMIC_CMP_SWAP()
[all …]
HDSystemZISelDAGToDAG.cpp435 if (Opcode == ISD::TRUNCATE) { in expandAddress()
609 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); in getAddressOperands()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp413 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
480 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); in LowerFormalArguments_32()
594 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
1312 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()
2687 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
2690 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); in LowerADDC_ADDE_SUBC_SUBE()
2693 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
2696 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); in LowerADDC_ADDE_SUBC_SUBE()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsISelLowering.cpp1969 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); in lowerFCOPYSIGN64()
1990 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); in lowerFCOPYSIGN64()
2846 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
2852 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
2858 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
2902 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); in UnpackFromArgumentSlot()
2907 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); in UnpackFromArgumentSlot()
2912 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); in UnpackFromArgumentSlot()

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