Searched refs:UADDO (Results 1 – 14 of 14) sorted by relevance
| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 228 SADDO, UADDO, enumerator
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| HD | SelectionDAG.h | 1086 case ISD::UADDO:
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeIntegerTypes.cpp | 124 case ISD::UADDO: in PromoteIntegerResult()
706 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_UADDSUBO()
1340 case ISD::UADDO: in ExpandIntegerResult()
1664 ISD::UADDO : ISD::USUBO, in ExpandIntRes_ADDSUB()
1672 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
2378 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? in ExpandIntRes_UADDSUBO()
2386 N->getOpcode () == ISD::UADDO ? in ExpandIntRes_UADDSUBO()
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| HD | SelectionDAGDumper.cpp | 218 case ISD::UADDO: return "uaddo"; in getOperationName()
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| HD | LegalizeDAG.cpp | 3721 case ISD::UADDO: in ExpandNode()
3725 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? in ExpandNode()
3733 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT; in ExpandNode()
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| HD | SelectionDAG.cpp | 2122 case ISD::UADDO: in computeKnownBits()
2577 case ISD::UADDO: in ComputeNumSignBits()
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| HD | SelectionDAGBuilder.cpp | 4859 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; in visitIntrinsicCall()
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| HD | DAGCombiner.cpp | 2610 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(), in visitUMULO()
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | R600ISelLowering.cpp | 97 setOperationAction(ISD::UADDO, MVT::i32, Custom); in R600TargetLowering()
587 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 1394 setOperationAction(ISD::UADDO, VT, Expand); in HexagonTargetLowering()
1482 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO, in HexagonTargetLowering()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 826 setOperationAction(ISD::UADDO, VT, Expand); in initActions()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 265 setOperationAction(ISD::UADDO, MVT::i32, Custom); in AArch64TargetLowering()
266 setOperationAction(ISD::UADDO, MVT::i64, Custom); in AArch64TargetLowering()
1292 case ISD::UADDO: in getAArch64XALUOOp()
1972 case ISD::UADDO: in LowerOperation()
3282 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBR_CC()
3761 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 680 setOperationAction(ISD::UADDO, MVT::i32, Custom); in ARMTargetLowering()
3319 case ISD::UADDO: in getARMXALUOOp()
3372 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT()
6610 case ISD::UADDO: in LowerOperation()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 1611 setOperationAction(ISD::UADDO, VT, Custom); in X86TargetLowering()
14104 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerSELECT()
14113 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; in LowerSELECT()
14604 Cond.getOperand(0).getOpcode() == ISD::UADDO || in LowerBRCOND()
14661 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerBRCOND()
14674 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; in LowerBRCOND()
17771 case ISD::UADDO: in LowerXALUO()
18605 case ISD::UADDO: in LowerOperation()
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