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Searched refs:UINT_TO_FP (Results 1 – 25 of 28) sorted by relevance

12

/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp106 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
109 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
111 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
113 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
115 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
117 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
119 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
121 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
123 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
125 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
[all …]
HDARMISelLowering.cpp105 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
110 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addTypeForNEON()
531 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
638 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
3969 case ISD::UINT_TO_FP: in LowerVectorINT_TO_FP()
3971 Opc = ISD::UINT_TO_FP; in LowerVectorINT_TO_FP()
6573 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); in LowerOperation()
9622 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) in PerformVDIVCombine()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp195 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
196 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
197 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
203 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
204 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
205 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
210 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
211 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
217 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
218 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
[all …]
HDAArch64ISelLowering.cpp196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
197 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
198 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
480 setTargetDAGCombine(ISD::UINT_TO_FP); in AArch64TargetLowering()
551 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
558 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote); in AArch64TargetLowering()
560 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote); in AArch64TargetLowering()
565 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote); in AArch64TargetLowering()
567 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote); in AArch64TargetLowering()
570 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp478 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, in getCastInstrCost()
479 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, in getCastInstrCost()
480 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, in getCastInstrCost()
481 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, in getCastInstrCost()
487 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, in getCastInstrCost()
488 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, in getCastInstrCost()
489 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, in getCastInstrCost()
490 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, in getCastInstrCost()
579 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, in getCastInstrCost()
622 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, in getCastInstrCost()
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HDX86InstrFragmentsSIMD.td404 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
406 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
HDX86ISelLowering.cpp173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); in X86TargetLowering()
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); in X86TargetLowering()
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); in X86TargetLowering()
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); in X86TargetLowering()
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); in X86TargetLowering()
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in X86TargetLowering()
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom); in X86TargetLowering()
925 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom); in X86TargetLowering()
[all …]
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h394 UINT_TO_FP, enumerator
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorOps.cpp335 case ISD::UINT_TO_FP: in LegalizeOp()
379 case ISD::UINT_TO_FP: in Promote()
443 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : in PromoteINT_TO_FP()
705 case ISD::UINT_TO_FP: in Expand()
HDLegalizeDAG.cpp1212 case ISD::UINT_TO_FP: in LegalizeOp()
2568 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); in ExpandLegalINT_TO_FP()
2574 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); in ExpandLegalINT_TO_FP()
2657 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP()
2658 OpToUse = ISD::UINT_TO_FP; in PromoteLegalINT_TO_FP()
3078 case ISD::UINT_TO_FP: in ExpandNode()
4102 if (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteNode()
4156 case ISD::UINT_TO_FP: in PromoteNode()
HDSelectionDAGDumper.cpp244 case ISD::UINT_TO_FP: return "uint_to_fp"; in getOperationName()
HDLegalizeVectorTypes.cpp98 case ISD::UINT_TO_FP: in ScalarizeVectorResult()
436 case ISD::UINT_TO_FP: in ScalarizeVectorOperand()
645 case ISD::UINT_TO_FP: in SplitVectorResult()
1383 case ISD::UINT_TO_FP: in SplitVectorOperand()
1987 case ISD::UINT_TO_FP: in WidenVectorResult()
2846 case ISD::UINT_TO_FP: in WidenVectorOperand()
HDLegalizeFloatTypes.cpp104 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break; in SoftenFloatResult()
922 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break; in ExpandFloatResult()
1782 case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break; in PromoteFloatResult()
HDDAGCombiner.cpp1381 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); in visit()
8507 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { in visitSINT_TO_FP()
8510 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); in visitSINT_TO_FP()
8556 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); in visitUINT_TO_FP()
8560 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && in visitUINT_TO_FP()
8591 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
11898 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { in reduceBuildVecConvertToConvertBuildVec()
11921 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) in reduceBuildVecConvertToConvertBuildVec()
HDLegalizeIntegerTypes.cpp880 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; in PromoteIntegerOperand()
2611 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; in ExpandIntegerOperand()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp311 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
347 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
643 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
1591 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2202 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2205 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2230 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo); in LowerUINT_TO_FP()
2233 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi); in LowerUINT_TO_FP()
HDSIISelLowering.cpp222 setTargetDAGCombine(ISD::UINT_TO_FP); in SITargetLowering()
1822 case ISD::UINT_TO_FP: { in PerformDAGCombine()
HDR600ISelLowering.cpp1831 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1832 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0), in PerformDAGCombine()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1557 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1558 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1559 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1567 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in HexagonTargetLowering()
1568 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in HexagonTargetLowering()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
110 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
616 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
756 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom); in PPCTargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1431 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1433 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
2810 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3215 case ISD::UINT_TO_FP: in ReplaceNodeResults()
/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp1579 case UIToFP: return ISD::UINT_TO_FP; in InstructionOpcodeToISD()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp282 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); in addMSAIntType()
1839 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp225 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); in SystemZTargetLowering()
226 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in SystemZTargetLowering()
349 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td435 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;

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