Searched refs:VREV32 (Results 1 – 5 of 5) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.h | 153 VREV32, // reverse elements within 32-bit words enumerator
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| HD | ARMScheduleSwift.td | 1579 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
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| HD | ARMISelLowering.cpp | 1124 case ARMISD::VREV32: return "ARMISD::VREV32"; in getTargetNodeName()
4468 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16); in lowerCTPOP32BitElements()
5668 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
5793 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
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| HD | ARMInstrNEON.td | 575 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
5968 // VREV32 : Vector Reverse elements within 32-bit words
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| /NextBSD/contrib/llvm/tools/clang/include/clang/Basic/ |
| HD | arm_neon.td | 757 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
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