1 //===-- RegisterContext_x86.h -----------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef liblldb_RegisterContext_x86_H_ 11 #define liblldb_RegisterContext_x86_H_ 12 13 //--------------------------------------------------------------------------- 14 // i386 gcc, dwarf, gdb enums 15 //--------------------------------------------------------------------------- 16 17 // Register numbers seen in eh_frame (eRegisterKindGCC) 18 // 19 // From Jason Molenda: "gcc registers" is the register numbering used in the eh_frame 20 // CFI. The only registers that are described in eh_frame CFI are those that are 21 // preserved across function calls aka callee-saved aka non-volatile. And none 22 // of the floating point registers on x86 are preserved across function calls. 23 // 24 // The only reason there is a "gcc register" and a "dwarf register" is because of a 25 // mistake years and years ago with i386 where they got esp and ebp 26 // backwards when they emitted the eh_frame instructions. Once there were 27 // binaries In The Wild using the reversed numbering, we had to stick with it 28 // forever. 29 enum 30 { 31 // 2nd parameter in DwarfRegNum() is regnum for exception handling on x86-32. 32 // See http://llvm.org/docs/WritingAnLLVMBackend.html#defining-a-register 33 gcc_eax_i386 = 0, 34 gcc_ecx_i386, 35 gcc_edx_i386, 36 gcc_ebx_i386, 37 38 // on Darwin esp & ebp are reversed in the eh_frame section for i386 (versus dwarf's reg numbering). 39 // To be specific: 40 // i386+darwin eh_frame: 4 is ebp, 5 is esp 41 // i386+everyone else eh_frame: 4 is esp, 5 is ebp 42 // i386 dwarf: 4 is esp, 5 is ebp 43 // lldb will get the darwin-specific eh_frame reg numberings from debugserver instead of here so we 44 // only encode the 4 == esp, 5 == ebp numbers in this generic header. 45 gcc_esp_i386, 46 gcc_ebp_i386, 47 gcc_esi_i386, 48 gcc_edi_i386, 49 gcc_eip_i386, 50 gcc_eflags_i386, 51 gcc_st0_i386 = 12, 52 gcc_st1_i386, 53 gcc_st2_i386, 54 gcc_st3_i386, 55 gcc_st4_i386, 56 gcc_st5_i386, 57 gcc_st6_i386, 58 gcc_st7_i386, 59 gcc_xmm0_i386 = 21, 60 gcc_xmm1_i386, 61 gcc_xmm2_i386, 62 gcc_xmm3_i386, 63 gcc_xmm4_i386, 64 gcc_xmm5_i386, 65 gcc_xmm6_i386, 66 gcc_xmm7_i386, 67 gcc_mm0_i386 = 29, 68 gcc_mm1_i386, 69 gcc_mm2_i386, 70 gcc_mm3_i386, 71 gcc_mm4_i386, 72 gcc_mm5_i386, 73 gcc_mm6_i386, 74 gcc_mm7_i386, 75 }; 76 77 // DWARF register numbers (eRegisterKindDWARF) 78 // Intel's x86 or IA-32 79 enum 80 { 81 // General Purpose Registers. 82 dwarf_eax_i386 = 0, 83 dwarf_ecx_i386, 84 dwarf_edx_i386, 85 dwarf_ebx_i386, 86 dwarf_esp_i386, 87 dwarf_ebp_i386, 88 dwarf_esi_i386, 89 dwarf_edi_i386, 90 dwarf_eip_i386, 91 dwarf_eflags_i386, 92 // Floating Point Registers 93 dwarf_st0_i386 = 11, 94 dwarf_st1_i386, 95 dwarf_st2_i386, 96 dwarf_st3_i386, 97 dwarf_st4_i386, 98 dwarf_st5_i386, 99 dwarf_st6_i386, 100 dwarf_st7_i386, 101 // SSE Registers 102 dwarf_xmm0_i386 = 21, 103 dwarf_xmm1_i386, 104 dwarf_xmm2_i386, 105 dwarf_xmm3_i386, 106 dwarf_xmm4_i386, 107 dwarf_xmm5_i386, 108 dwarf_xmm6_i386, 109 dwarf_xmm7_i386, 110 // MMX Registers 111 dwarf_mm0_i386 = 29, 112 dwarf_mm1_i386, 113 dwarf_mm2_i386, 114 dwarf_mm3_i386, 115 dwarf_mm4_i386, 116 dwarf_mm5_i386, 117 dwarf_mm6_i386, 118 dwarf_mm7_i386, 119 dwarf_fctrl_i386 = 37, // x87 control word 120 dwarf_fstat_i386 = 38, // x87 status word 121 dwarf_mxcsr_i386 = 39, 122 dwarf_es_i386 = 40, 123 dwarf_cs_i386 = 41, 124 dwarf_ss_i386 = 42, 125 dwarf_ds_i386 = 43, 126 dwarf_fs_i386 = 44, 127 dwarf_gs_i386 = 45 128 129 // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and 130 // then differentiate based on size of the register. 131 }; 132 133 // Register numbers GDB uses (eRegisterKindGDB) 134 // 135 // From Jason Molenda: The "gdb numbers" are what you would see in the stabs debug format. 136 enum 137 { 138 gdb_eax_i386, 139 gdb_ecx_i386, 140 gdb_edx_i386, 141 gdb_ebx_i386, 142 gdb_esp_i386, 143 gdb_ebp_i386, 144 gdb_esi_i386, 145 gdb_edi_i386, 146 gdb_eip_i386, 147 gdb_eflags_i386, 148 gdb_cs_i386, 149 gdb_ss_i386, 150 gdb_ds_i386, 151 gdb_es_i386, 152 gdb_fs_i386, 153 gdb_gs_i386, 154 gdb_st0_i386 = 16, 155 gdb_st1_i386, 156 gdb_st2_i386, 157 gdb_st3_i386, 158 gdb_st4_i386, 159 gdb_st5_i386, 160 gdb_st6_i386, 161 gdb_st7_i386, 162 gdb_fctrl_i386, // FPU Control Word 163 gdb_fstat_i386, // FPU Status Word 164 gdb_ftag_i386, // FPU Tag Word 165 gdb_fiseg_i386, // FPU IP Selector 166 gdb_fioff_i386, // FPU IP Offset 167 gdb_foseg_i386, // FPU Operand Pointer Selector 168 gdb_fooff_i386, // FPU Operand Pointer Offset 169 gdb_fop_i386, // Last Instruction Opcode 170 gdb_xmm0_i386 = 32, 171 gdb_xmm1_i386, 172 gdb_xmm2_i386, 173 gdb_xmm3_i386, 174 gdb_xmm4_i386, 175 gdb_xmm5_i386, 176 gdb_xmm6_i386, 177 gdb_xmm7_i386, 178 gdb_mxcsr_i386 = 40, 179 gdb_ymm0h_i386, 180 gdb_ymm1h_i386, 181 gdb_ymm2h_i386, 182 gdb_ymm3h_i386, 183 gdb_ymm4h_i386, 184 gdb_ymm5h_i386, 185 gdb_ymm6h_i386, 186 gdb_ymm7h_i386, 187 gdb_mm0_i386, 188 gdb_mm1_i386, 189 gdb_mm2_i386, 190 gdb_mm3_i386, 191 gdb_mm4_i386, 192 gdb_mm5_i386, 193 gdb_mm6_i386, 194 gdb_mm7_i386, 195 }; 196 197 //--------------------------------------------------------------------------- 198 // AMD x86_64, AMD64, Intel EM64T, or Intel 64 gcc, dwarf, gdb enums 199 //--------------------------------------------------------------------------- 200 201 // GCC and DWARF Register numbers (eRegisterKindGCC & eRegisterKindDWARF) 202 // This is the spec I used (as opposed to x86-64-abi-0.99.pdf): 203 // http://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf 204 enum 205 { 206 // GP Registers 207 gcc_dwarf_rax_x86_64 = 0, 208 gcc_dwarf_rdx_x86_64, 209 gcc_dwarf_rcx_x86_64, 210 gcc_dwarf_rbx_x86_64, 211 gcc_dwarf_rsi_x86_64, 212 gcc_dwarf_rdi_x86_64, 213 gcc_dwarf_rbp_x86_64, 214 gcc_dwarf_rsp_x86_64, 215 // Extended GP Registers 216 gcc_dwarf_r8_x86_64 = 8, 217 gcc_dwarf_r9_x86_64, 218 gcc_dwarf_r10_x86_64, 219 gcc_dwarf_r11_x86_64, 220 gcc_dwarf_r12_x86_64, 221 gcc_dwarf_r13_x86_64, 222 gcc_dwarf_r14_x86_64, 223 gcc_dwarf_r15_x86_64, 224 // Return Address (RA) mapped to RIP 225 gcc_dwarf_rip_x86_64 = 16, 226 // SSE Vector Registers 227 gcc_dwarf_xmm0_x86_64 = 17, 228 gcc_dwarf_xmm1_x86_64, 229 gcc_dwarf_xmm2_x86_64, 230 gcc_dwarf_xmm3_x86_64, 231 gcc_dwarf_xmm4_x86_64, 232 gcc_dwarf_xmm5_x86_64, 233 gcc_dwarf_xmm6_x86_64, 234 gcc_dwarf_xmm7_x86_64, 235 gcc_dwarf_xmm8_x86_64, 236 gcc_dwarf_xmm9_x86_64, 237 gcc_dwarf_xmm10_x86_64, 238 gcc_dwarf_xmm11_x86_64, 239 gcc_dwarf_xmm12_x86_64, 240 gcc_dwarf_xmm13_x86_64, 241 gcc_dwarf_xmm14_x86_64, 242 gcc_dwarf_xmm15_x86_64, 243 // Floating Point Registers 244 gcc_dwarf_st0_x86_64 = 33, 245 gcc_dwarf_st1_x86_64, 246 gcc_dwarf_st2_x86_64, 247 gcc_dwarf_st3_x86_64, 248 gcc_dwarf_st4_x86_64, 249 gcc_dwarf_st5_x86_64, 250 gcc_dwarf_st6_x86_64, 251 gcc_dwarf_st7_x86_64, 252 // MMX Registers 253 gcc_dwarf_mm0_x86_64 = 41, 254 gcc_dwarf_mm1_x86_64, 255 gcc_dwarf_mm2_x86_64, 256 gcc_dwarf_mm3_x86_64, 257 gcc_dwarf_mm4_x86_64, 258 gcc_dwarf_mm5_x86_64, 259 gcc_dwarf_mm6_x86_64, 260 gcc_dwarf_mm7_x86_64, 261 // Control and Status Flags Register 262 gcc_dwarf_rflags_x86_64 = 49, 263 // selector registers 264 gcc_dwarf_es_x86_64 = 50, 265 gcc_dwarf_cs_x86_64, 266 gcc_dwarf_ss_x86_64, 267 gcc_dwarf_ds_x86_64, 268 gcc_dwarf_fs_x86_64, 269 gcc_dwarf_gs_x86_64, 270 // Floating point control registers 271 gcc_dwarf_mxcsr_x86_64 = 64, // Media Control and Status 272 gcc_dwarf_fctrl_x86_64, // x87 control word 273 gcc_dwarf_fstat_x86_64, // x87 status word 274 // Upper Vector Registers 275 gcc_dwarf_ymm0h_x86_64 = 67, 276 gcc_dwarf_ymm1h_x86_64, 277 gcc_dwarf_ymm2h_x86_64, 278 gcc_dwarf_ymm3h_x86_64, 279 gcc_dwarf_ymm4h_x86_64, 280 gcc_dwarf_ymm5h_x86_64, 281 gcc_dwarf_ymm6h_x86_64, 282 gcc_dwarf_ymm7h_x86_64, 283 gcc_dwarf_ymm8h_x86_64, 284 gcc_dwarf_ymm9h_x86_64, 285 gcc_dwarf_ymm10h_x86_64, 286 gcc_dwarf_ymm11h_x86_64, 287 gcc_dwarf_ymm12h_x86_64, 288 gcc_dwarf_ymm13h_x86_64, 289 gcc_dwarf_ymm14h_x86_64, 290 gcc_dwarf_ymm15h_x86_64, 291 // AVX2 Vector Mask Registers 292 // gcc_dwarf_k0_x86_64 = 118, 293 // gcc_dwarf_k1_x86_64, 294 // gcc_dwarf_k2_x86_64, 295 // gcc_dwarf_k3_x86_64, 296 // gcc_dwarf_k4_x86_64, 297 // gcc_dwarf_k5_x86_64, 298 // gcc_dwarf_k6_x86_64, 299 // gcc_dwarf_k7_x86_64, 300 }; 301 302 // GDB Register numbers (eRegisterKindGDB) 303 enum 304 { 305 // GP Registers 306 gdb_rax_x86_64 = 0, 307 gdb_rbx_x86_64, 308 gdb_rcx_x86_64, 309 gdb_rdx_x86_64, 310 gdb_rsi_x86_64, 311 gdb_rdi_x86_64, 312 gdb_rbp_x86_64, 313 gdb_rsp_x86_64, 314 // Extended GP Registers 315 gdb_r8_x86_64, 316 gdb_r9_x86_64, 317 gdb_r10_x86_64, 318 gdb_r11_x86_64, 319 gdb_r12_x86_64, 320 gdb_r13_x86_64, 321 gdb_r14_x86_64, 322 gdb_r15_x86_64, 323 // Return Address (RA) mapped to RIP 324 gdb_rip_x86_64, 325 // Control and Status Flags Register 326 gdb_rflags_x86_64, 327 gdb_cs_x86_64, 328 gdb_ss_x86_64, 329 gdb_ds_x86_64, 330 gdb_es_x86_64, 331 gdb_fs_x86_64, 332 gdb_gs_x86_64, 333 // Floating Point Registers 334 gdb_st0_x86_64, 335 gdb_st1_x86_64, 336 gdb_st2_x86_64, 337 gdb_st3_x86_64, 338 gdb_st4_x86_64, 339 gdb_st5_x86_64, 340 gdb_st6_x86_64, 341 gdb_st7_x86_64, 342 gdb_fctrl_x86_64, 343 gdb_fstat_x86_64, 344 gdb_ftag_x86_64, 345 gdb_fiseg_x86_64, 346 gdb_fioff_x86_64, 347 gdb_foseg_x86_64, 348 gdb_fooff_x86_64, 349 gdb_fop_x86_64, 350 // SSE Vector Registers 351 gdb_xmm0_x86_64 = 40, 352 gdb_xmm1_x86_64, 353 gdb_xmm2_x86_64, 354 gdb_xmm3_x86_64, 355 gdb_xmm4_x86_64, 356 gdb_xmm5_x86_64, 357 gdb_xmm6_x86_64, 358 gdb_xmm7_x86_64, 359 gdb_xmm8_x86_64, 360 gdb_xmm9_x86_64, 361 gdb_xmm10_x86_64, 362 gdb_xmm11_x86_64, 363 gdb_xmm12_x86_64, 364 gdb_xmm13_x86_64, 365 gdb_xmm14_x86_64, 366 gdb_xmm15_x86_64, 367 // Floating point control registers 368 gdb_mxcsr_x86_64 = 56, 369 gdb_ymm0h_x86_64, 370 gdb_ymm1h_x86_64, 371 gdb_ymm2h_x86_64, 372 gdb_ymm3h_x86_64, 373 gdb_ymm4h_x86_64, 374 gdb_ymm5h_x86_64, 375 gdb_ymm6h_x86_64, 376 gdb_ymm7h_x86_64, 377 gdb_ymm8h_x86_64, 378 gdb_ymm9h_x86_64, 379 gdb_ymm10h_x86_64, 380 gdb_ymm11h_x86_64, 381 gdb_ymm12h_x86_64, 382 gdb_ymm13h_x86_64, 383 gdb_ymm14h_x86_64, 384 gdb_ymm15h_x86_64 385 }; 386 387 //--------------------------------------------------------------------------- 388 // Generic floating-point registers 389 //--------------------------------------------------------------------------- 390 391 struct MMSReg 392 { 393 uint8_t bytes[10]; 394 uint8_t pad[6]; 395 }; 396 397 struct XMMReg 398 { 399 uint8_t bytes[16]; // 128-bits for each XMM register 400 }; 401 402 // i387_fxsave_struct 403 struct FXSAVE 404 { 405 uint16_t fctrl; // FPU Control Word (fcw) 406 uint16_t fstat; // FPU Status Word (fsw) 407 uint16_t ftag; // FPU Tag Word (ftw) 408 uint16_t fop; // Last Instruction Opcode (fop) 409 union 410 { 411 struct 412 { 413 uint64_t fip; // Instruction Pointer 414 uint64_t fdp; // Data Pointer 415 } x86_64; 416 struct 417 { 418 uint32_t fioff; // FPU IP Offset (fip) 419 uint32_t fiseg; // FPU IP Selector (fcs) 420 uint32_t fooff; // FPU Operand Pointer Offset (foo) 421 uint32_t foseg; // FPU Operand Pointer Selector (fos) 422 } i386_;// Added _ in the end to avoid error with gcc defining i386 in some cases 423 } ptr; 424 uint32_t mxcsr; // MXCSR Register State 425 uint32_t mxcsrmask; // MXCSR Mask 426 MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes 427 XMMReg xmm[16]; // 16*16 bytes for each XMM-reg = 256 bytes 428 uint32_t padding[24]; 429 }; 430 431 //--------------------------------------------------------------------------- 432 // Extended floating-point registers 433 //--------------------------------------------------------------------------- 434 435 struct YMMHReg 436 { 437 uint8_t bytes[16]; // 16 * 8 bits for the high bytes of each YMM register 438 }; 439 440 struct YMMReg 441 { 442 uint8_t bytes[32]; // 16 * 16 bits for each YMM register 443 }; 444 445 struct YMM 446 { 447 YMMReg ymm[16]; // assembled from ymmh and xmm registers 448 }; 449 450 struct XSAVE_HDR 451 { 452 uint64_t xstate_bv; // OS enabled xstate mask to determine the extended states supported by the processor 453 uint64_t reserved1[2]; 454 uint64_t reserved2[5]; 455 } __attribute__((packed)); 456 457 // x86 extensions to FXSAVE (i.e. for AVX processors) 458 struct XSAVE 459 { 460 FXSAVE i387; // floating point registers typical in i387_fxsave_struct 461 XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the following extensions are usable 462 YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes are in FXSAVE.xmm for compatibility with SSE) 463 // Slot any extensions to the register file here 464 } __attribute__((packed, aligned (64))); 465 466 // Floating-point registers 467 struct FPR 468 { 469 // Thread state for the floating-point unit of the processor read by ptrace. 470 union XSTATE 471 { 472 FXSAVE fxsave; // Generic floating-point registers. 473 XSAVE xsave; // x86 extended processor state. 474 } xstate; 475 }; 476 477 //--------------------------------------------------------------------------- 478 // ptrace PTRACE_GETREGSET, PTRACE_SETREGSET structure 479 //--------------------------------------------------------------------------- 480 481 struct IOVEC 482 { 483 void *iov_base; // pointer to XSAVE 484 size_t iov_len; // sizeof(XSAVE) 485 }; 486 487 #endif 488