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Searched refs:ZEXTLOAD (Results 1 – 25 of 29) sorted by relevance

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/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h784 ZEXTLOAD, enumerator
HDSelectionDAGNodes.h2271 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
141 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
467 SDValue Load = DAG.getLoad(ISD::UNINDEXED, ISD::ZEXTLOAD, in LowerParameter()
481 ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerParameter()
1479 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT, in performUCharToFloatCombine()
HDR600ISelLowering.cpp138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
1495 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
HDAMDGPUISelLowering.cpp224 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
233 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
HDAMDGPUInstructions.td189 return L->getExtensionType() == ISD::ZEXTLOAD ||
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp933 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteOperand()
1155 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteLoad()
3023 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
3037 case ISD::ZEXTLOAD: in visitAND()
3046 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
3089 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, in visitAND()
3093 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
3105 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, in visitAND()
3128 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
3166 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) { in visitAND()
[all …]
HDLegalizeDAG.cpp527 HiExtType = ISD::ZEXTLOAD; in ExpandUnalignedLoad()
532 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), in ExpandUnalignedLoad()
550 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, in ExpandUnalignedLoad()
972 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
987 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
1013 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), in LegalizeLoadOps()
1054 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, in LegalizeLoadOps()
HDSelectionDAGDumper.cpp480 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
HDLegalizeVectorOps.cpp593 case ISD::ZEXTLOAD: in ExpandLoad()
HDLegalizeIntegerTypes.cpp1982 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
2032 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
HDTargetLowering.cpp1350 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { in SimplifySetCC()
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp152 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp133 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); in XCoreTargetLowering()
470 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp245 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
278 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
1607 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) { in adjustSubwordCmp()
1618 ISD::ZEXTLOAD); in adjustSubwordCmp()
1647 case ISD::ZEXTLOAD: in isNaturalMemoryOperand()
1800 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) || in adjustICmpTruncate()
HDSystemZOperators.td388 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsISelLowering.cpp240 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MipsTargetLowering()
418 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
2216 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); in lowerLOAD()
3708 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal); in X86TargetLowering()
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal); in X86TargetLowering()
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal); in X86TargetLowering()
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal); in X86TargetLowering()
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal); in X86TargetLowering()
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal); in X86TargetLowering()
1184 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal); in X86TargetLowering()
1185 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal); in X86TargetLowering()
1186 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal); in X86TargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp227 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in NVPTXTargetLowering()
2184 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
2310 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1092 Ext = ISD::ZEXTLOAD; in LowerLOAD()
1439 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
HDHexagonISelDAGToDAG.cpp380 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp87 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
484 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in PPCTargetLowering()
2292 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
2315 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
6404 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
11390 LD->getExtensionType() == ISD::ZEXTLOAD)) in isZExtFree()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td689 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp602 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1251 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD && in getAArch64Cmp()
2210 ExtType = ISD::ZEXTLOAD; in LowerFormalArguments()
8491 ExtType = ISD::ZEXTLOAD; in checkValueWidth()

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