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Searched refs:addLiveIn (Results 1 – 25 of 52) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIPrepareScratchRegs.cpp82 Entry->addLiveIn(ScratchPtrPreloadReg); in runOnMachineFunction()
85 Entry->addLiveIn(ScratchOffsetPreloadReg); in runOnMachineFunction()
123 MBB.addLiveIn(ScratchOffsetReg); in runOnMachineFunction()
170 MBB.addLiveIn(ScratchOffsetReg); in runOnMachineFunction()
HDSIMachineFunctionInfo.cpp62 BI->addLiveIn(LaneVGPR); in getSpilledReg()
HDSIISelLowering.cpp585 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass); in LowerFormalArguments()
586 MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass); in LowerFormalArguments()
643 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass); in LowerFormalArguments()
651 Reg = MF.addLiveIn(Reg, RC); in LowerFormalArguments()
664 Reg = MF.addLiveIn(Reg, RC); in LowerFormalArguments()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelDAGToDAG.cpp149 MF.getRegInfo().addLiveIn(Mips::T9_64); in initGlobalBaseReg()
150 MBB.addLiveIn(Mips::T9_64); in initGlobalBaseReg()
177 MF.getRegInfo().addLiveIn(Mips::T9); in initGlobalBaseReg()
178 MBB.addLiveIn(Mips::T9); in initGlobalBaseReg()
212 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
213 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
HDMips16FrameLowering.cpp127 EntryBlock->addLiveIn(Reg); in spillCalleeSavedRegisters()
HDMipsSEFrameLowering.cpp475 MBB.addLiveIn(ABI.GetEhDataReg(I)); in emitPrologue()
600 EntryBlock->addLiveIn(Reg); in spillCalleeSavedRegisters()
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430FrameLowering.cpp78 I->addLiveIn(MSP430::FP); in emitPrologue()
200 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZFrameLowering.cpp120 MBB.addLiveIn(GPR64); in addSavedGPR()
204 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
380 I->addLiveIn(SystemZ::R11D); in emitPrologue()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMFrameLowering.cpp979 MBB.addLiveIn(Reg); in emitPushInst()
1184 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
1202 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
1214 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
1223 MBB.addLiveIn(NextReg); in emitAlignedDPRCS2Spills()
1919 AllocMBB->addLiveIn(*i); in adjustForSegmentedStacks()
1920 GetMBB->addLiveIn(*i); in adjustForSegmentedStacks()
1921 McrMBB->addLiveIn(*i); in adjustForSegmentedStacks()
1922 PrevStackMBB->addLiveIn(*i); in adjustForSegmentedStacks()
1923 PostStackMBB->addLiveIn(*i); in adjustForSegmentedStacks()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86FrameLowering.cpp787 I->addLiveIn(MachineFramePtr); in emitPrologue()
1369 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
1382 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
1551 allocMBB->addLiveIn(*i); in adjustForSegmentedStacks()
1552 checkMBB->addLiveIn(*i); in adjustForSegmentedStacks()
1556 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D); in adjustForSegmentedStacks()
1827 stackCheckMBB->addLiveIn(*I); in adjustForHiPEPrologue()
1828 incStackMBB->addLiveIn(*I); in adjustForHiPEPrologue()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreFrameLowering.cpp263 MBB.addLiveIn(XCore::LR); in emitPrologue()
288 MBB.addLiveIn(SpillList[i].Reg); in emitPrologue()
432 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
/NextBSD/contrib/llvm/lib/CodeGen/
HDMachineRegisterInfo.cpp389 EntryMBB->addLiveIn(LiveIns[i].first); in EmitLiveInCopies()
393 EntryMBB->addLiveIn(LiveIns[i].first); in EmitLiveInCopies()
HDVirtRegMap.cpp268 LiveIn[i]->addLiveIn(SubReg); in addMBBLiveIns()
280 LiveIn[i]->addLiveIn(PhysReg); in addMBBLiveIns()
HDMachineBasicBlock.cpp341 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { in addLiveIn() function in MachineBasicBlock
368 addLiveIn(PhysReg); in addLiveIn()
813 NMBB->addLiveIn(*I); in SplitCriticalEdge()
HDCallingConvLower.cpp243 unsigned VReg = MF.addLiveIn(PReg, RC); in analyzeMustTailForwardedRegisters()
HDMachineFunction.cpp439 unsigned MachineFunction::addLiveIn(unsigned PReg, in addLiveIn() function in MachineFunction
457 MRI.addLiveIn(PReg, VReg); in addLiveIn()
HDBranchFolding.cpp399 NewMBB->addLiveIn(i); in MaintainLiveIns()
1835 TBB->addLiveIn(Def); in HoistCommonCodeInSuccs()
1836 FBB->addLiveIn(Def); in HoistCommonCodeInSuccs()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonCFGOptimizer.cpp221 LayoutSucc->addLiveIn(NewLiveIn[i]); in runOnMachineFunction()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineBasicBlock.h321 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
334 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
HDMachineFunction.h331 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcFrameLowering.cpp240 MBB->addLiveIn(reg - SP::I0 + SP::O0); in remapRegsForLeafProc()
HDSparcISelLowering.cpp380 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
395 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
406 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
519 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); in LowerFormalArguments_32()
568 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
639 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); in LowerFormalArguments_64()
2506 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64FrameLowering.cpp799 MBB.addLiveIn(Reg1); in spillCalleeSavedRegisters()
800 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp2872 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
2960 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_32SVR4()
2979 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); in LowerFormalArguments_32SVR4()
3172 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
3208 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
3232 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
3245 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
3272 VReg = MF.addLiveIn(FPR[FPR_idx], in LowerFormalArguments_64SVR4()
3277 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
3290 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
[all …]
/NextBSD/contrib/llvm/lib/CodeGen/MIRParser/
HDMIRParser.cpp330 MBB.addLiveIn(Reg); in initializeMachineBasicBlock()

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