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Searched refs:addRegisterClass (Results 1 – 16 of 16) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp41 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
42 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
44 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
45 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
47 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
48 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
50 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass); in SITargetLowering()
51 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
52 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); in SITargetLowering()
54 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); in SITargetLowering()
[all …]
HDR600ISelLowering.cpp36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1306 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering()
1307 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
1308 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa in HexagonTargetLowering()
1309 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba in HexagonTargetLowering()
1310 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1311 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1312 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1313 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1314 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1315 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp92 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering()
94 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering()
95 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering()
97 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass); in SystemZTargetLowering()
98 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass); in SystemZTargetLowering()
100 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering()
101 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering()
103 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); in SystemZTargetLowering()
106 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
107 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); in MipsSETargetLowering()
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering()
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering()
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
247 addRegisterClass(Ty, RC); in addMSAIntType()
296 addRegisterClass(Ty, RC); in addMSAFloatType()
HDMips16ISelLowering.cpp128 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
509 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
510 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
511 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
512 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
581 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass); in PPCTargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp133 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering()
134 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
135 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
136 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering()
137 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering()
138 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp144 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
145 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
146 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
148 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
517 addRegisterClass(MVT::f32, &X86::FR32RegClass); in X86TargetLowering()
518 addRegisterClass(MVT::f64, &X86::FR64RegClass); in X86TargetLowering()
551 addRegisterClass(MVT::f32, &X86::FR32RegClass); in X86TargetLowering()
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering()
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering()
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass); in X86TargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp65 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
66 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1376 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1377 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1378 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1379 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1381 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp96 addRegisterClass(MVT::i64, &BPF::GPRRegClass); in BPFTargetLowering()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp91 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
92 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
95 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
96 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
97 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
98 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
102 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
103 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
699 addRegisterClass(VT, &AArch64::FPR64RegClass); in addDRTypeForNEON()
704 addRegisterClass(VT, &AArch64::FPR128RegClass); in addQRTypeForNEON()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetLowering.h1274 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { in addRegisterClass() function
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp148 addRegisterClass(VT, &ARM::DPRRegClass); in addDRTypeForNEON()
153 addRegisterClass(VT, &ARM::DPairRegClass); in addQRTypeForNEON()
396 addRegisterClass(MVT::i32, &ARM::tGPRRegClass); in ARMTargetLowering()
398 addRegisterClass(MVT::i32, &ARM::GPRRegClass); in ARMTargetLowering()
401 addRegisterClass(MVT::f32, &ARM::SPRRegClass); in ARMTargetLowering()
402 addRegisterClass(MVT::f64, &ARM::DPRRegClass); in ARMTargetLowering()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp77 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()