Searched refs:areMemAccessesTriviallyDisjoint (Results 1 – 8 of 8) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64InstrInfo.h | 56 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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| HD | AArch64LoadStoreOptimizer.cpp | 497 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
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| HD | AArch64InstrInfo.cpp | 602 AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, in areMemAccessesTriviallyDisjoint() function in AArch64InstrInfo
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | SIInstrInfo.h | 131 bool areMemAccessesTriviallyDisjoint(
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| HD | SIInstrInfo.cpp | 1088 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, in areMemAccessesTriviallyDisjoint() function in SIInstrInfo
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetInstrInfo.h | 1252 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonExpandCondsets.cpp | 856 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI)) in canMoveMemTo()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | ScheduleDAGInstrs.cpp | 529 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA)) in MIsNeedChainEdge()
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