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Searched refs:i16 (Results 1 – 25 of 108) sorted by relevance

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/NextBSD/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
HDtst.signedkeyspos.d66 @i16["mouse", (short)-2] = sum(-2);
67 @i16["dog", (short)-2] = sum(-22);
68 @i16["cat", (short)-2] = sum(-222);
69 @i16["mouse", (short)-1] = sum(-1);
70 @i16["dog", (short)-1] = sum(-11);
71 @i16["cat", (short)-1] = sum(-111);
72 @i16["mouse", (short)0] = sum(0);
73 @i16["dog", (short)0] = sum(10);
74 @i16["cat", (short)0] = sum(100);
75 @i16["mouse", (short)1] = sum(1);
[all …]
HDtst.signedkeys.d101 @i16[(short)-2] = sum(-2);
102 @i16[(short)-1] = sum(-1);
103 @i16[(short)0] = sum(0);
104 @i16[(short)1] = sum(1);
105 @i16[(short)2] = sum(2);
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp66 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
82 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in MSP430TargetLowering()
98 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
99 setOperationAction(ISD::SHL, MVT::i16, Custom); in MSP430TargetLowering()
100 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
103 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
104 setOperationAction(ISD::ROTR, MVT::i16, Expand); in MSP430TargetLowering()
105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in MSP430TargetLowering()
[all …]
HDMSP430ISelDAGToDAG.cpp265 MVT::i16, AM.Disp, in SelectAddr()
268 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, in SelectAddr()
271 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/); in SelectAddr()
273 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/); in SelectAddr()
278 Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16); in SelectAddr()
314 case MVT::i16: in isValidIndexedLoad()
339 case MVT::i16: in SelectIndexedLoad()
347 VT, MVT::i16, MVT::Other, in SelectIndexedLoad()
362 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); in SelectIndexedBinOp()
367 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0); in SelectIndexedBinOp()
[all …]
HDMSP430CallingConv.td19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
30 // Promote i8 arguments to i16.
31 CCIfType<[i8], CCPromoteToType<i16>>,
35 CCIfType<[i16], CCAssignToStack<2, 2>>
HDMSP430InstrInfo.td20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
26 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
74 def memsrc : Operand<i16> {
79 def memdst : Operand<i16> {
102 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
103 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
305 def : Pat<(i16 (zext def8:$src)),
306 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
315 [(store (i16 imm:$src), addr:$dst)]>;
[all …]
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDValueTypes.td25 def i16 : ValueType<16 , 3>; // 16-bit integer value
49 def v1i16 : ValueType<16 , 26>; // 1 x i16 vector value
50 def v2i16 : ValueType<32 , 27>; // 2 x i16 vector value
51 def v4i16 : ValueType<64 , 28>; // 4 x i16 vector value
52 def v8i16 : ValueType<128, 29>; // 8 x i16 vector value
53 def v16i16 : ValueType<256, 30>; // 16 x i16 vector value
54 def v32i16 : ValueType<512, 31>; // 32 x i16 vector value
HDMachineValueType.h41 i16 = 3, // This is a 16 bit integer value enumerator
303 case v32i16: return i16; in getVectorElementType()
401 case i16 : in getSizeInBits()
516 return MVT::i16; in getIntegerVT()
547 case MVT::i16: in getVectorVT()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86CallingConv.td30 // the way LLVM does multiple return values -- a return of {i16,i8} would end
33 // values into an i16 (which uses AX, and thus AL:AH).
39 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
103 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
132 CCIfType<[i8, i16], CCPromoteToType<i32>>,
179 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
188 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
255 // Promote i1/i8/i16 arguments to i32.
256 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
327 // Promote i1/i8/i16 arguments to i32.
[all …]
HDX86ISelDAGToDAG.cpp651 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in MatchLoadInAddress()
654 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in MatchLoadInAddress()
1353 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in SelectVectorAddr()
1355 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in SelectVectorAddr()
1402 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in SelectAddr()
1404 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in SelectAddr()
1818 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 && in getAtomicLoadArithTargetConstant()
1879 case MVT::i16: in SelectAtomicLoadArith()
2026 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 && in isLoadIncOrDecStore()
2090 if (LdVT == MVT::i16) return X86::DEC16m; in getFusedLdStOpcode()
[all …]
HDX86InstrCompiler.td257 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
295 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
302 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
349 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
361 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
379 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
394 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
497 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
800 (add (atomic_load_16 addr:$dst), (i16 1)),
805 (add (atomic_load_16 addr:$dst), (i16 -1)),
[all …]
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelDAGToDAG.cpp692 case MVT::i16: in SelectLoad()
720 case MVT::i16: in SelectLoad()
749 case MVT::i16: in SelectLoad()
772 case MVT::i16: in SelectLoad()
801 case MVT::i16: in SelectLoad()
824 case MVT::i16: in SelectLoad()
932 case MVT::i16: in SelectLoadVector()
956 case MVT::i16: in SelectLoadVector()
985 case MVT::i16: in SelectLoadVector()
1009 case MVT::i16: in SelectLoadVector()
[all …]
HDNVPTXISelLowering.cpp134 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
145 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand); in NVPTXTargetLowering()
152 setOperationAction(ISD::BR_CC, MVT::i16, Expand); in NVPTXTargetLowering()
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in NVPTXTargetLowering()
185 setOperationAction(ISD::ROTL, MVT::i16, Expand); in NVPTXTargetLowering()
186 setOperationAction(ISD::ROTR, MVT::i16, Expand); in NVPTXTargetLowering()
189 setOperationAction(ISD::BSWAP, MVT::i16, Expand); in NVPTXTargetLowering()
253 setOperationAction(ISD::CTLZ, MVT::i16, Legal); in NVPTXTargetLowering()
256 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal); in NVPTXTargetLowering()
259 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in NVPTXTargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsCallingConv.td78 // Promote i8/i16 arguments to i32.
79 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
93 // Promote i1/i8/i16 return values to i32.
94 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
129 CCIfType<[i8, i16, i32, i64],
134 CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>,
165 CCIfType<[i8, i16, i32, i64],
170 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
199 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
201 CCIfType<[i8, i16, i32, i64],
[all …]
HDMipsFastISel.cpp292 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) in materializeInt()
557 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
569 if (VT == MVT::i8 || VT == MVT::i16) in isLoadTypeLegal()
712 case MVT::i16: { in emitLoad()
771 case MVT::i16: in emitStore()
1113 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) || in processCallArgs()
1225 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) in finishCall()
1282 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
1349 if (VT == MVT::i16) { in fastLowerIntrinsicCall()
1491 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) in selectRet()
[all …]
/NextBSD/contrib/netbsd-tests/include/
HDt_inttypes.c41 int16_t i16 = 0; in ATF_TC_BODY() local
75 PRINT(PRId16, i16); in ATF_TC_BODY()
90 PRINT(PRIi16, i16); in ATF_TC_BODY()
166 SCAN(SCNd16, i16); in ATF_TC_BODY()
181 SCAN(SCNi16, i16); in ATF_TC_BODY()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCFastISel.cpp283 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) { in isLoadTypeLegal()
477 case MVT::i16: in PPCEmitLoad()
620 case MVT::i16: in PPCEmitStore()
821 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
842 case MVT::i16: in PPCEmitCmp()
1002 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && in SelectIToFP()
1024 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) { in SelectIToFP()
1165 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1405 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) in finishCall()
1429 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) { in finishCall()
[all …]
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp173 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, in getCastInstrCost()
174 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 }, in getCastInstrCost()
175 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, in getCastInstrCost()
176 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 }, in getCastInstrCost()
204 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
205 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
206 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
207 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
229 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 }, in getCastInstrCost()
233 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 }, in getCastInstrCost()
HDARMCallingConv.td24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
42 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
102 // Promote i8/i16 arguments to i32.
103 CCIfType<[i8, i16], CCPromoteToType<i32>>,
115 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
132 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
HDARMFastISel.cpp511 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) in ARMMaterializeInt()
749 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isLoadTypeLegal()
867 case MVT::i16: in ARMSimplifyAddress()
987 case MVT::i16: in ARMEmitLoad()
1111 case MVT::i16: in ARMEmitStore()
1383 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1419 case MVT::i16: in ARMEmitCmp()
1563 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
1570 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) { in SelectIToFP()
1716 else if (VT == MVT::i16) in SelectDiv()
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.td50 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
52 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
77 CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>,
131 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
133 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
159 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16", CCAssignToStack<2, 2>>,
174 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
191 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
192 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
243 // Promote i8/i16/i32 arguments to i64.
[all …]
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFCallingConv.td19 // Promote i8/i16/i32 args to i64
20 CCIfType<[ i8, i16, i32 ], CCPromoteToType<i64>>,
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreCallingConv.td28 // Promote i8/i16 arguments to i32.
29 CCIfType<[i8, i16], CCPromoteToType<i32>>,
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp152 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { in CC_Hexagon_VarArg()
189 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { in CC_Hexagon()
270 LocVT == MVT::i16) { in RetCC_Hexagon()
671 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { in getIndexedAddressParts()
900 if (RegVT == MVT::i8 || RegVT == MVT::i16 || in LowerFormalArguments()
1040 (RHSVT == MVT::i8 || RHSVT == MVT::i16) && in LowerSETCC()
1041 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) { in LowerSETCC()
1099 LoadNode->getPointerInfo(), MVT::i16, in LowerLOAD()
1108 LoadNode->getPointerInfo(), MVT::i16, in LowerLOAD()
1121 LoadNode->getPointerInfo(), MVT::i16, in LowerLOAD()
[all …]
/NextBSD/contrib/netbsd-tests/ipf/
HDt_filter_parse.sh101 test_case i16 itest text ipf
127 atf_add_test_case i16

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