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/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcInstrAliases.td66 // b<cond> $imm
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
70 // b<cond>,a $imm
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
74 // b<cond> %icc, $imm
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
[all …]
HDSparc.h117 inline static unsigned HI22(int64_t imm) { in HI22() argument
118 return (unsigned)((imm >> 10) & ((1 << 22)-1)); in HI22()
121 inline static unsigned LO10(int64_t imm) { in LO10() argument
122 return (unsigned)(imm & 0x3FF); in LO10()
125 inline static unsigned HIX22(int64_t imm) { in HIX22() argument
126 return HI22(~imm); in HIX22()
129 inline static unsigned LOX10(int64_t imm) { in LOX10() argument
130 return ~LO10(~imm); in LOX10()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIIntrinsics.td28 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
31 llvm_i32_ty, // inst_offset(imm)
32 llvm_i32_ty, // dfmt(imm)
33 llvm_i32_ty, // nfmt(imm)
34 llvm_i32_ty, // offen(imm)
35 llvm_i32_ty, // idxen(imm)
36 llvm_i32_ty, // glc(imm)
37 llvm_i32_ty, // slc(imm)
38 llvm_i32_ty], // tfe(imm)
47 llvm_i32_ty, // inst_offset(imm)
[all …]
HDR600Instructions.td217 (imm),
224 (imm),
231 (imm),
238 (imm),
245 (imm),
252 (imm),
386 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
387 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
388 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
389 (i32 imm:$DST_SEL_W),
[all …]
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonOperands.td67 def s32ImmPred : PatLeaf<(i32 imm), [{
72 def s32_0ImmPred : PatLeaf<(i32 imm), [{
77 def s31_1ImmPred : PatLeaf<(i32 imm), [{
82 def s30_2ImmPred : PatLeaf<(i32 imm), [{
87 def s29_3ImmPred : PatLeaf<(i32 imm), [{
92 def s22_10ImmPred : PatLeaf<(i32 imm), [{
97 def s8_24ImmPred : PatLeaf<(i32 imm), [{
102 def s16_16ImmPred : PatLeaf<(i32 imm), [{
107 def s26_6ImmPred : PatLeaf<(i32 imm), [{
112 def s16ImmPred : PatLeaf<(i32 imm), [{
[all …]
/NextBSD/contrib/gcc/
HDtree-ssanames.c124 use_operand_p imm; in make_ssa_name() local
160 imm = &(SSA_NAME_IMM_USE_NODE (t)); in make_ssa_name()
161 imm->use = NULL; in make_ssa_name()
162 imm->prev = imm; in make_ssa_name()
163 imm->next = imm; in make_ssa_name()
164 imm->stmt = t; in make_ssa_name()
208 use_operand_p imm = &(SSA_NAME_IMM_USE_NODE (var)); in release_ssa_name() local
213 while (imm->next != imm) in release_ssa_name()
214 delink_imm_use (imm->next); in release_ssa_name()
219 imm->prev = imm; in release_ssa_name()
[all …]
HDtree-flow-inline.h402 end_readonly_imm_use_p (imm_use_iterator *imm) in end_readonly_imm_use_p() argument
404 return (imm->imm_use == imm->end_p); in end_readonly_imm_use_p()
409 first_readonly_imm_use (imm_use_iterator *imm, tree var) in first_readonly_imm_use() argument
413 imm->end_p = &(SSA_NAME_IMM_USE_NODE (var)); in first_readonly_imm_use()
414 imm->imm_use = imm->end_p->next; in first_readonly_imm_use()
416 imm->iter_node.next = imm->imm_use->next; in first_readonly_imm_use()
418 if (end_readonly_imm_use_p (imm)) in first_readonly_imm_use()
420 return imm->imm_use; in first_readonly_imm_use()
425 next_readonly_imm_use (imm_use_iterator *imm) in next_readonly_imm_use() argument
427 use_operand_p old = imm->imm_use; in next_readonly_imm_use()
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HDtree-phinodes.c229 use_operand_p imm; in make_phi_node() local
230 imm = &(PHI_ARG_IMM_USE_NODE (phi, i)); in make_phi_node()
231 imm->use = &(PHI_ARG_DEF_TREE (phi, i)); in make_phi_node()
232 imm->prev = NULL; in make_phi_node()
233 imm->next = NULL; in make_phi_node()
234 imm->stmt = phi; in make_phi_node()
250 use_operand_p imm; in release_phi_node() local
251 imm = &(PHI_ARG_IMM_USE_NODE (phi, x)); in release_phi_node()
252 delink_imm_use (imm); in release_phi_node()
285 use_operand_p imm, old_imm; in resize_phi_node() local
[all …]
/NextBSD/contrib/binutils/opcodes/
HDsh-dis.c498 int imm = 0; in print_insn_sh() local
527 imm = (nibs[2] << 4) | (nibs[3]); in print_insn_sh()
528 if (imm & 0x80) in print_insn_sh()
529 imm |= ~0xff; in print_insn_sh()
530 imm = ((char) imm) * 2 + 4; in print_insn_sh()
533 imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); in print_insn_sh()
534 if (imm & 0x800) in print_insn_sh()
535 imm |= ~0xfff; in print_insn_sh()
536 imm = imm * 2 + 4; in print_insn_sh()
541 imm = nibs[3] & 0x7; in print_insn_sh()
[all …]
HDarm-dis.c1764 int imm; in print_insn_coprocessor() local
1766 imm = (given & 0xf) | ((given & 0xe0) >> 1); in print_insn_coprocessor()
1769 if (imm & 0x40) in print_insn_coprocessor()
1770 imm |= -(1 << 7); in print_insn_coprocessor()
1772 func (stream, "%d", imm); in print_insn_coprocessor()
2976 int imm; in print_insn_arm() local
2978 imm = (given & 0xf) | ((given & 0xfff00) >> 4); in print_insn_arm()
2979 func (stream, "%d", imm); in print_insn_arm()
3170 long imm = (given & 0x07c0) >> 6; in print_insn_thumb16() local
3171 if (imm == 0) in print_insn_thumb16()
[all …]
/NextBSD/contrib/llvm/tools/clang/lib/Headers/
HDemmintrin.h831 #define _mm_slli_si128(a, imm) __extension__ ({ \ argument
834 ((imm)&0xF0) ? 0 : 16 - ((imm)&0xF), \
835 ((imm)&0xF0) ? 0 : 17 - ((imm)&0xF), \
836 ((imm)&0xF0) ? 0 : 18 - ((imm)&0xF), \
837 ((imm)&0xF0) ? 0 : 19 - ((imm)&0xF), \
838 ((imm)&0xF0) ? 0 : 20 - ((imm)&0xF), \
839 ((imm)&0xF0) ? 0 : 21 - ((imm)&0xF), \
840 ((imm)&0xF0) ? 0 : 22 - ((imm)&0xF), \
841 ((imm)&0xF0) ? 0 : 23 - ((imm)&0xF), \
842 ((imm)&0xF0) ? 0 : 24 - ((imm)&0xF), \
[all …]
HDf16cintrin.h41 #define _mm_cvtps_ph(a, imm) __extension__ ({ \ argument
43 (__m128i)__builtin_ia32_vcvtps2ph((__v4sf)__a, (imm)); })
45 #define _mm256_cvtps_ph(a, imm) __extension__ ({ \ argument
47 (__m128i)__builtin_ia32_vcvtps2ph256((__v8sf)__a, (imm)); })
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFInstrInfo.td53 def i64immSExt32 : PatLeaf<(imm),
68 def BPF_CC_EQ : PatLeaf<(imm),
70 def BPF_CC_NE : PatLeaf<(imm),
72 def BPF_CC_GE : PatLeaf<(imm),
74 def BPF_CC_GT : PatLeaf<(imm),
76 def BPF_CC_GTU : PatLeaf<(imm),
78 def BPF_CC_GEU : PatLeaf<(imm),
104 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
105 !strconcat(OpcodeStr, "i\t$dst, $imm goto $BrDst"),
106 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMips64r6InstrInfo.td51 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
52 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
135 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
136 (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
137 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
139 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
140 (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
141 (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
144 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
146 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
[all …]
HDMicroMipsInstrInfo.td283 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
284 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
351 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
352 !strconcat(opstr, "\t$rd, $rs, $imm"),
358 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
359 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
364 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
365 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
368 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
369 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
[all …]
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMInstrThumb2.td45 def t2_so_reg : Operand<i32>, // reg imm
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
62 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
70 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
94 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
102 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
113 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
129 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
135 def imm1_255_neg : PatLeaf<(i32 imm), [{
140 def imm0_255_not : PatLeaf<(i32 imm), [{
[all …]
HDARMInstrInfo.td324 def imm_neg_XFORM : SDNodeXForm<imm, [{
329 def imm_not_XFORM : SDNodeXForm<imm, [{
344 def hi16 : SDNodeXForm<imm, [{
349 def lo16AllZero : PatLeaf<(i32 imm), [{
485 def rot_imm_XFORM: SDNodeXForm<imm, [{
498 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
523 def so_reg_reg : Operand<i32>, // reg reg imm
534 def so_reg_imm : Operand<i32>, // reg imm
545 def shift_so_reg_reg : Operand<i32>, // reg reg imm
556 def shift_so_reg_imm : Operand<i32>, // reg reg imm
[all …]
/NextBSD/sys/mips/mips/
HDdb_trace.c297 args[0] = kdbpeek((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
302 args[1] = kdbpeek((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
307 args[2] = kdbpeek((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
312 args[3] = kdbpeek((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
317 ra = kdbpeek((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
331 args[0] = kdbpeekd((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
336 args[1] = kdbpeekd((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
341 args[2] = kdbpeekd((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
346 args[3] = kdbpeekd((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
351 ra = kdbpeekd((int *)(sp + (short)i.IType.imm)); in stacktrace_subr()
[all …]
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrInfo.td54 let MIOperandInfo = (ops i32imm:$imm);
235 def SHL32 : SDNodeXForm<imm, [{
236 // Transformation function: 31 - imm
240 def SRL32 : SDNodeXForm<imm, [{
241 // Transformation function: 32 - imm
246 def LO16 : SDNodeXForm<imm, [{
251 def HI16 : SDNodeXForm<imm, [{
256 def HA16 : SDNodeXForm<imm, [{
261 def MB : SDNodeXForm<imm, [{
268 def ME : SDNodeXForm<imm, [{
[all …]
HDPPCInstrHTM.td19 def HTM_get_imm : SDNodeXForm<imm, [{
99 TBEGIN (HTM_get_imm imm:$R)), sub_eq),
103 (TEND (HTM_get_imm imm:$R))>;
110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
113 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
119 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
131 (TSR (HTM_get_imm imm:$L))>;
/NextBSD/contrib/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp1147 unsigned imm = fieldFromInstruction(Val, 7, 5); in DecodeSORegImmOperand() local
1169 if (Shift == ARM_AM::ror && imm == 0) in DecodeSORegImmOperand()
1172 unsigned Op = Shift | (imm << 3); in DecodeSORegImmOperand()
1333 unsigned imm = fieldFromInstruction(Insn, 0, 8); in DecodeCopMemInstruction() local
1420 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); in DecodeCopMemInstruction()
1421 Inst.addOperand(MCOperand::createImm(imm)); in DecodeCopMemInstruction()
1439 imm |= U << 8; in DecodeCopMemInstruction()
1444 Inst.addOperand(MCOperand::createImm(imm)); in DecodeCopMemInstruction()
1483 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeAddrMode2IdxInstruction() local
1566 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); in DecodeAddrMode2IdxInstruction() local
[all …]
/NextBSD/crypto/openssl/crypto/perlasm/
HDx86asm.pl87 { my($dst,$src,$imm)=@_;
89 { &::data_byte(0x66,0x0f,0x3a,0x16,0xc0|($2<<3)|$regrm{$1},$imm); }
95 { my($dst,$src,$imm)=@_;
97 { &::data_byte(0x66,0x0f,0x3a,0x22,0xc0|($1<<3)|$regrm{$2},$imm); }
111 { my($dst,$src,$imm)=@_;
113 { &::data_byte(0x66,0x0f,0x3a,0x0f,0xc0|($1<<3)|$2,$imm); }
119 { my($dst,$src,$imm)=@_;
121 { &::data_byte(0x66,0x0f,0x3a,0x44,0xc0|($1<<3)|$2,$imm); }
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.td411 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
412 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
413 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
414 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
415 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
416 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
443 // Final group of aliases covers true "mov $Rd, $imm" cases.
457 def : InstAlias<"mov $Rd, $imm",
458 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
485 [(set GPR32:$dst, imm:$src)]>,
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrShiftRotate.td36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
50 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
90 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
94 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
98 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
102 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
142 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
145 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
[all …]
/NextBSD/contrib/llvm/lib/Target/Hexagon/Disassembler/
HDHexagonDisassembler.cpp388 uint64_t imm = SignExtend64<16>(tmp); in s16ImmDecoder() local
389 MI.addOperand(MCOperand::createImm(imm)); in s16ImmDecoder()
395 uint64_t imm = SignExtend64<12>(tmp); in s12ImmDecoder() local
396 MI.addOperand(MCOperand::createImm(imm)); in s12ImmDecoder()
402 uint64_t imm = SignExtend64<11>(tmp); in s11_0ImmDecoder() local
403 MI.addOperand(MCOperand::createImm(imm)); in s11_0ImmDecoder()
409 uint64_t imm = SignExtend64<12>(tmp); in s11_1ImmDecoder() local
410 MI.addOperand(MCOperand::createImm(imm)); in s11_1ImmDecoder()
416 uint64_t imm = SignExtend64<13>(tmp); in s11_2ImmDecoder() local
417 MI.addOperand(MCOperand::createImm(imm)); in s11_2ImmDecoder()
[all …]

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