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/NextBSD/contrib/binutils/gas/config/
HDtc-arm.c307 unsigned long instruction; member
6155 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); in encode_arm_vfp_reg()
6159 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); in encode_arm_vfp_reg()
6163 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); in encode_arm_vfp_reg()
6167 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); in encode_arm_vfp_reg()
6171 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); in encode_arm_vfp_reg()
6175 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); in encode_arm_vfp_reg()
6189 inst.instruction |= SHIFT_ROR << 5; in encode_arm_shift()
6192 inst.instruction |= inst.operands[i].shift_kind << 5; in encode_arm_shift()
6195 inst.instruction |= SHIFT_BY_REG; in encode_arm_shift()
[all …]
HDtc-score.c141 unsigned long instruction; member
871 inst.instruction |= reg << shift; in reg_required_here()
927 if ((((inst.instruction >> 15) & 0x10) == 0) in do_rdrsrs()
928 && (((inst.instruction >> 10) & 0x10) == 0) in do_rdrsrs()
929 && (((inst.instruction >> 20) & 0x10) == 0) in do_rdrsrs()
931 && (((inst.instruction >> 20) & 0xf) == ((inst.instruction >> 15) & 0xf))) in do_rdrsrs()
933 inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) in do_rdrsrs()
934 | (((inst.instruction >> 15) & 0xf) << 8); in do_rdrsrs()
1248 inst.instruction |= 0x8000000; in data_op2()
1249 inst.instruction |= ((inst.reloc.exp.X_add_number >> 16) << 1) & 0x1fffe; in data_op2()
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HDtc-cr16.c66 const inst *instruction; variable
896 switch (instruction->size) in process_label_constant()
934 switch (instruction->size) in process_label_constant()
1397 if (streq (cr16_no_op_insn[i], instruction->mnemonic)) in parse_insn()
1714 if ((instruction->size > 2) && (shift == WORD_SHIFT)) in print_constant()
1734 if (instruction->size == 2) in print_constant()
1758 if ((instruction->size > 2) && (shift == WORD_SHIFT)) in print_constant()
1812 if (instruction->size == 3) in print_operand()
1863 if (instruction->size > 1) in print_operand()
1867 if (instruction->size == 2) in print_operand()
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/NextBSD/contrib/binutils/opcodes/
HDcr16-dis.c84 const inst *instruction; variable
133 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) in get_number_of_operands()
309 unsigned long mask = SBM (instruction->match_bits); in build_mask()
323 instruction = &cr16_instruction[NUMOPCODES - 2]; in match_opcode()
326 while (instruction >= cr16_instruction) in match_opcode()
329 if ((doubleWord & mask) == BIN (instruction->match, in match_opcode()
330 instruction->match_bits)) in match_opcode()
333 instruction--; in match_opcode()
346 if ((instruction->size == 3) && a->size >= 16) in make_argument()
413 else if (instruction->size == 2) in make_argument()
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/NextBSD/contrib/subversion/subversion/libsvn_fs_x/
HDreps.c443 instruction_t instruction; in add_new_text() local
451 instruction.offset = (apr_int32_t)builder->text->len; in add_new_text()
452 instruction.count = (apr_uint32_t)len; in add_new_text()
453 APR_ARRAY_PUSH(builder->instructions, instruction_t) = instruction; in add_new_text()
464 for (offset = instruction.offset; in add_new_text()
475 else if (builder->hash.offsets[idx] >= instruction.offset) in add_new_text()
530 instruction_t instruction; in svn_fs_x__reps_add() local
552 instruction.offset = (apr_int32_t)(offset - prefix_match); in svn_fs_x__reps_add()
553 instruction.count = (apr_uint32_t)(prefix_match + postfix_match + in svn_fs_x__reps_add()
555 APR_ARRAY_PUSH(builder->instructions, instruction_t) = instruction; in svn_fs_x__reps_add()
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/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetItinerary.td11 // which should be implemented by each target that uses instruction
13 // tables for each instruction class. They are most appropriate for
23 // during scheduling and has an affect instruction order based on availability
44 // the execution of an instruction. Cycles represents the number of
68 // required to complete an instruction. Itineraries are represented as lists of
69 // instruction stages.
73 // Instruction itinerary classes - These values represent 'named' instruction
75 // instructions across chip sets. An instruction uses the same itinerary class
77 // instruction information.
84 // instruction itinerary class (name) to its itinerary data.
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HDTarget.td117 // require larger instruction encodings.
175 // meaning it takes a single instruction to perform the copying. A negative
192 // model instruction operand constraints, and should have isAllocatable = 0.
329 string AsmString = ""; // The .s format to print the instruction with.
331 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
336 // instruction pattern.
345 // Size - Size of encoded instruction, or zero if the size cannot be determined
349 // DecoderNamespace - The "namespace" in which this instruction exists, on
353 // Code size, for instruction selection.
361 // instruction.
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/NextBSD/contrib/xz/src/liblzma/simple/
HDia64.c41 uint64_t instruction = 0; in ia64_code() local
44 instruction += (uint64_t)( in ia64_code()
48 uint64_t inst_norm = instruction >> bit_res; in ia64_code()
73 instruction &= (1 << bit_res) - 1; in ia64_code()
74 instruction |= (inst_norm << bit_res); in ia64_code()
78 instruction in ia64_code()
/NextBSD/contrib/llvm/tools/lldb/include/lldb/Core/
HDEmulateInstruction.h359 EmulateInstruction *instruction) const;
363 typedef size_t (*ReadMemoryCallback) (EmulateInstruction *instruction,
370 typedef size_t (*WriteMemoryCallback) (EmulateInstruction *instruction,
377 typedef bool (*ReadRegisterCallback) (EmulateInstruction *instruction,
382 typedef bool (*WriteRegisterCallback) (EmulateInstruction *instruction,
532 ReadMemoryFrame (EmulateInstruction *instruction,
540 WriteMemoryFrame (EmulateInstruction *instruction,
548 ReadRegisterFrame (EmulateInstruction *instruction,
555 WriteRegisterFrame (EmulateInstruction *instruction,
562 ReadMemoryDefault (EmulateInstruction *instruction,
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/NextBSD/contrib/llvm/tools/lldb/source/Plugins/UnwindAssembly/InstEmulation/
HDUnwindAssemblyInstEmulation.h76 ReadMemory (lldb_private::EmulateInstruction *instruction,
84 WriteMemory (lldb_private::EmulateInstruction *instruction,
92 ReadRegister (lldb_private::EmulateInstruction *instruction,
98 WriteRegister (lldb_private::EmulateInstruction *instruction,
113 WriteMemory (lldb_private::EmulateInstruction *instruction,
120 ReadRegister (lldb_private::EmulateInstruction *instruction,
125 WriteRegister (lldb_private::EmulateInstruction *instruction,
HDUnwindAssemblyInstEmulation.cpp335 UnwindAssemblyInstEmulation::ReadMemory (EmulateInstruction *instruction, in ReadMemory() argument
351 context.Dump(strm, instruction); in ReadMemory()
359 UnwindAssemblyInstEmulation::WriteMemory (EmulateInstruction *instruction, in WriteMemory() argument
367 …return ((UnwindAssemblyInstEmulation *)baton)->WriteMemory (instruction, context, addr, dst, dst_l… in WriteMemory()
372 UnwindAssemblyInstEmulation::WriteMemory (EmulateInstruction *instruction, in WriteMemory() argument
380 instruction->GetArchitecture ().GetByteOrder(), in WriteMemory()
381 instruction->GetArchitecture ().GetAddressByteSize()); in WriteMemory()
392 context.Dump(strm, instruction); in WriteMemory()
454 UnwindAssemblyInstEmulation::ReadRegister (EmulateInstruction *instruction, in ReadRegister() argument
461 … return ((UnwindAssemblyInstEmulation *)baton)->ReadRegister (instruction, reg_info, reg_value); in ReadRegister()
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMips16InstrFormats.td34 // This class does not depend on the instruction size
70 // For 32 bit extended instruction forms.
100 // Format I instruction class in Mips : <|opcode|imm11|>
115 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
132 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
249 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
271 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
293 // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
315 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrFormats.td30 // Maintain list of valid subtargets for each instruction.
55 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
56 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
57 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
58 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
59 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
106 // Only A-type instruction in first slot or nothing.
150 // If an instruction is valid on a subtarget, set the corresponding
152 // By default, instruction is valid on all subtargets.
194 // Definition of the instruction class NOT CHANGED.
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/NextBSD/contrib/binutils/gas/doc/
HDc-alpha.texi45 assemble an instruction which will not execute on the target processor,
46 the assembler may either expand the instruction as a macro or issue an
162 The relocation is placed at the end of the instruction like so:
174 Used with an @code{ldq} instruction to load the address of a symbol
185 the @code{literal} instruction must also be marked with @code{lituse}
186 relocations. This is because the original @code{literal} instruction
187 may be deleted or transformed into another instruction.
196 Used with any memory format instruction (e.g.@: @code{ldl}) to indicate
198 instruction must be zero. During relaxation, the code may be altered
202 Used with a register branch format instruction (e.g.@: @code{jsr}) to
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HDc-i386.texi82 This option specifies an instruction set architecture for generating
182 source operand, such as the @samp{enter} instruction, do @emph{not} have
193 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
196 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
210 instruction
226 @cindex i386 instruction naming
227 @cindex instruction naming, i386
228 @cindex x86-64 instruction naming
229 @cindex instruction naming, x86-64
234 no suffix is specified by an instruction then @code{@value{AS}} tries to
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HDc-arc.texi45 Base instruction set.
49 Jump-and-link (jl) instruction. No requirement of an instruction between
63 Software interrupt (swi) instruction.
217 Name of the extension instruction
231 conditional suffixes and flag setting by the extension instruction.
232 It is also possible to specify that an instruction sets the flags and
236 Determines the syntax class for the instruction. It can have the
254 of a three-operand instruction must be an immediate (i.e., the result
262 syntax. For example, if the source code contains an instruction like:
283 The above specifies an extension instruction called mp64 which has 3 operands,
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/NextBSD/contrib/gcc/doc/
HDcfg.texi16 intermediate code representation (the RTL or @code{tree} instruction
46 underlying instruction stream. The chain of basic blocks is updated
73 instruction (the @dfn{head}) and the last instruction (the @dfn{tail})
74 or @dfn{end} of the instruction stream contained in a basic block. In
84 In the RTL representation of a function, the instruction stream
88 that the instruction stream consists of linear regions, making such
90 kind of note that may appear in the instruction stream contained in a
91 basic block. The instruction stream of a basic block always follows a
94 instruction or last instruction before following @code{CODE_LABEL} or
96 the instruction stream of a basic block.
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HDmd.texi11 A machine description has two parts: a file of instruction patterns
15 instruction that the target machine supports (or at least each instruction
24 * Patterns:: How to write instruction patterns.
65 instruction patterns.
104 @cindex instruction patterns
107 Each instruction pattern contains an incomplete RTL expression, with pieces
116 An optional name. The presence of a name indicate that this instruction
119 the instruction patterns with those names, if the names are defined
123 where the name should go. Nameless instruction patterns are never
132 for identifying the instruction in RTL dumps; it is entirely equivalent
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/NextBSD/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/
HDEmulationStateARM.h54 ReadPseudoMemory (lldb_private::EmulateInstruction *instruction,
62 WritePseudoMemory (lldb_private::EmulateInstruction *instruction,
70 ReadPseudoRegister (lldb_private::EmulateInstruction *instruction,
76 WritePseudoRegister (lldb_private::EmulateInstruction *instruction,
/NextBSD/contrib/llvm/tools/lldb/source/Core/
HDEmulateInstruction.cpp285 EmulateInstruction::ReadMemoryFrame (EmulateInstruction *instruction, in ReadMemoryFrame() argument
307 EmulateInstruction::WriteMemoryFrame (EmulateInstruction *instruction, in WriteMemoryFrame() argument
330 EmulateInstruction::ReadRegisterFrame (EmulateInstruction *instruction, in ReadRegisterFrame() argument
343 EmulateInstruction::WriteRegisterFrame (EmulateInstruction *instruction, in WriteRegisterFrame() argument
357 EmulateInstruction::ReadMemoryDefault (EmulateInstruction *instruction, in ReadMemoryDefault() argument
366 context.Dump (strm, instruction); in ReadMemoryDefault()
373 EmulateInstruction::WriteMemoryDefault (EmulateInstruction *instruction, in WriteMemoryDefault() argument
382 context.Dump (strm, instruction); in WriteMemoryDefault()
388 EmulateInstruction::ReadRegisterDefault (EmulateInstruction *instruction, in ReadRegisterDefault() argument
406 EmulateInstruction::WriteRegisterDefault (EmulateInstruction *instruction, in WriteRegisterDefault() argument
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPC.td62 "Enable the MFOCRF instruction">;
64 "Enable the fsqrt instruction">;
66 "Enable the fcpsgn instruction">;
68 "Enable the fre instruction">;
70 "Enable the fres instruction">;
72 "Enable the frsqrte instruction">;
74 "Enable the frsqrtes instruction">;
78 "Enable the stfiwx instruction">;
80 "Enable the lfiwax instruction">;
86 "Enable the isel instruction">;
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/NextBSD/contrib/gcc/config/arm/
HDREADME-interworking5 calls between code compiled for the ARM instruction set and code
6 compiled for the Thumb instruction set and vice versa. This document
12 compiling for the ARM instruction set and the Thumb instruction set
55 instruction.
57 * Normal function calls can just use the BL instruction. The
61 * Calls via function pointers should use the BX instruction if
69 the mov instruction will not set the bottom bit of the lr
228 Switching between the ARM and Thumb instruction sets is accomplished
229 via the BX instruction which takes as an argument a register name.
232 instruction processing is enabled, otherwise ARM instruction
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/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXInstrFormats.td15 // Vector instruction type enum
45 // with 0 meaning the operation is not a surface instruction. For example,
46 // if IsSuld == 2, then the instruction is a suld instruction with vector size
/NextBSD/sys/mips/rmi/dev/sec/
HDrmilib.c151 desc->ctl_desc.instruction = 0; in xlr_sec_setup()
1008 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_BYPASS); in xlr_sec_setup_cipher()
1013 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_DES); in xlr_sec_setup_cipher()
1017 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_3DES); in xlr_sec_setup_cipher()
1022 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES128); in xlr_sec_setup_cipher()
1027 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES192); in xlr_sec_setup_cipher()
1032 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES256); in xlr_sec_setup_cipher()
1036 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_ARC4); in xlr_sec_setup_cipher()
1037 SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_KEYLEN, in xlr_sec_setup_cipher()
1039 SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_LOADSTATE, in xlr_sec_setup_cipher()
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/NextBSD/crypto/openssl/doc/crypto/
HDOPENSSL_ia32cap.pod16 EDX:ECX register pair after executing CPUID instruction with EAX=1
27 =item bit #19 denoting availability of CLFLUSH instruction;
44 =item bit #33 denoting availability of PCLMULQDQ instruction;
50 =item bit #57 denoting AES-NI instruction set extension;
56 =item bit #62 denoting availability of RDRAND instruction;
92 =item bit #64+18 denoting availability of RDSEED instruction;

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