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Searched refs:isAllocatable (Results 1 – 24 of 24) sorted by relevance

/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetRegisterInfo.cpp89 if (!RC || RC->isAllocatable()) in getAllocatableClass()
99 if (SubRC->isAllocatable()) in getAllocatableClass()
133 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
150 if ((*I)->isAllocatable()) in getAllocatableSet()
HDMachineRegisterInfo.cpp43 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
95 assert(RegClass->isAllocatable() && in createVirtualRegister()
426 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
HDRegAllocFast.cpp527 !RC->contains(Hint) || !MRI->isAllocatable(Hint))) in allocVirtReg()
804 if (MRI->isAllocatable(*I)) in AllocateBasicBlock()
943 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
1032 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
HDCalcSpillWeights.cpp160 if (hweight > bestPhys && mri.isAllocatable(hint)) in calculateSpillWeightAndHint()
HDAggressiveAntiDepBreaker.cpp634 if (!MRI.isAllocatable(NewSuperReg)) continue; in FindSuitableFreeRegisters()
832 if (!MRI.isAllocatable(AntiDepReg)) { in BreakAntiDependencies()
HDMachineVerifier.cpp187 bool isAllocatable(unsigned Reg) { in isAllocatable() function
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); in isAllocatable()
514 if (isAllocatable(reg) && !MBB->isLandingPad() && in visitMachineBasicBlockBefore()
HDCriticalAntiDepBreaker.cpp547 if (!MRI.isAllocatable(AntiDepReg)) in BreakAntiDependencies()
HDMachineCSE.cpp285 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i])) in PhysRegDefsReach()
HDRegAllocPBQP.cpp425 if (!MF.getRegInfo().isAllocatable(DstReg)) in apply()
HDRegisterPressure.cpp359 else if (MRI->isAllocatable(Reg)) { in pushRegUnits()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreRegisterInfo.td58 let isAllocatable = 0;
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetRegisterInfo.h102 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
HDTarget.td190 // isAllocatable - Specify that the register class can be used for virtual
192 // model instruction operand constraints, and should have isAllocatable = 0.
193 bit isAllocatable = 1;
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonRegisterInfo.td187 let Size = 32, isAllocatable = 0 in
194 let Size = 64, isAllocatable = 0 in
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600RegisterInfo.td159 let isAllocatable = 0 in {
205 } // End isAllocatable = 0
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86RegisterInfo.td441 let isAllocatable = 0;
454 let isAllocatable = 0;
458 let isAllocatable = 0;
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCRegisterInfo.td353 let isAllocatable = 0;
356 let isAllocatable = 0;
HDPPCRegisterInfo.cpp120 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); in getCalleeSavedRegs()
/NextBSD/contrib/llvm/include/llvm/MC/
HDMCRegisterInfo.h95 bool isAllocatable() const { return Allocatable; } in isAllocatable() function
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineRegisterInfo.h759 bool isAllocatable(unsigned PhysReg) const { in isAllocatable() function
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcRegisterInfo.td253 let isAllocatable = 0;
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsRegisterInfo.td26 bit isAllocatable = 0;
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMRegisterInfo.td265 let isAllocatable = 0;
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64RegisterInfo.td209 let isAllocatable = 0;