| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeDAG.cpp | 2650 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP() 2657 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP() 2693 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { in PromoteLegalFP_TO_INT() 2699 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { in PromoteLegalFP_TO_INT() 2858 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && in ExpandBitCount() 2859 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) in ExpandBitCount() 3368 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode() 3508 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode() 3535 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) && in ExpandNode() 3536 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) { in ExpandNode() [all …]
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| HD | TargetLowering.cpp | 1062 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); in SimplifyDemandedBits() 1063 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits() 2747 isOperationLegalOrCustom(ISD::MULHS, VT)) in BuildSDIV() 2751 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) in BuildSDIV() 2825 isOperationLegalOrCustom(ISD::MULHU, VT)) in BuildUDIV() 2828 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) in BuildUDIV() 2879 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT); in expandMUL() 2880 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT); in expandMUL() 2881 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT); in expandMUL() 2882 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT); in expandMUL() [all …]
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| HD | LegalizeVectorOps.cpp | 469 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { in PromoteFP_TO_INT() 473 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) { in PromoteFP_TO_INT() 984 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { in ExpandFNEG()
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| HD | DAGCombiner.cpp | 561 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) in isNegatibleForFree() 2492 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) { in SimplifyNodeWithTwoResults() 3455 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) in MatchBSwapHWord() 3457 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) in MatchBSwapHWord() 3849 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT); in MatchRotatePosNeg() 3866 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); in MatchRotate() 3867 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); in MatchRotate() 4107 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0.getOpcode() == ISD::SHL in visitXOR() 4527 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && in visitSRA() 4528 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && in visitSRA() [all …]
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| HD | LegalizeIntegerTypes.cpp | 408 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT() 1394 TLI.isOperationLegalOrCustom(ISD::ADDC, in ExpandShiftByConstant() 1644 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? in ExpandIntRes_ADDSUB() 1663 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? in ExpandIntRes_ADDSUB()
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| HD | SelectionDAGBuilder.cpp | 2304 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) && in visitSelect() 7461 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || in areJTsAllowed() 7462 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other); in areJTsAllowed()
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| HD | SelectionDAG.cpp | 4109 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) && in FindOptimalMemOpLowering() 4113 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::f64) && in FindOptimalMemOpLowering()
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | BasicTTIImpl.h | 183 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || in shouldBuildLookupTables() 184 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other); in shouldBuildLookupTables() 191 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCCTRLoops.cpp | 373 if (TLI->isOperationLegalOrCustom(Opcode, VTy)) in mightUseCTR() 376 TLI->isOperationLegalOrCustom(Opcode, VTy.getScalarType())) in mightUseCTR()
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| HD | PPCISelLowering.cpp | 6196 isOperationLegalOrCustom(Op.getOpcode(), in canReuseLoadAddress()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | CodeGenPrepare.cpp | 955 if (TLI.isOperationLegalOrCustom( in SinkShiftAndTruncate() 2281 return TLI.isOperationLegalOrCustom( in isPromotedInstructionLegal() 4235 TLI.isOperationLegalOrCustom( in shouldPromote()
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetLowering.h | 556 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { in isOperationLegalOrCustom() function
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 3957 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap() 5265 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT)) in buildFromShuffleMostly() 14524 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) && in LowerExtendedLoad() 21851 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT)) in XFormVExtractWithShuffleIntoLoad() 22654 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) in PerformSELECTCombine()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 6586 isOperationLegalOrCustom(ISD::FMA, VT) && in isProfitableToHoist()
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