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Searched refs:lanes (Results 1 – 25 of 43) sorted by relevance

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/NextBSD/sys/contrib/octeon-sdk/
HDcvmx-helper-ilk.c320 int lanes = 0; in __cvmx_helper_ilk_link_get() local
373 lanes = cvmx_pop(ilk_rxx_cfg1.s.rx_bdry_lock_ena); in __cvmx_helper_ilk_link_get()
378 result.s.speed *= lanes; in __cvmx_helper_ilk_link_get()
HDcvmx-helper-xaui.c375 int lanes; in __cvmx_helper_xaui_link_get() local
380 lanes = (qlm_cfg.s.qlm_cfg == 7) ? 2 : 4; in __cvmx_helper_xaui_link_get()
381 result.s.speed *= lanes; in __cvmx_helper_xaui_link_get()
/NextBSD/sys/dev/drm2/i915/
HDintel_bios.c531 switch (edp_link_params->lanes) { in parse_edp()
533 dev_priv->edp.lanes = 1; in parse_edp()
536 dev_priv->edp.lanes = 2; in parse_edp()
540 dev_priv->edp.lanes = 4; in parse_edp()
HDintel_bios.h463 u8 lanes:4; member
/NextBSD/sys/gnu/dts/arm/
HDspear1310.dtsi93 num-lanes = <1>;
111 num-lanes = <1>;
129 num-lanes = <1>;
HDtegra30-beaver.dts33 nvidia,num-lanes = <2>;
37 nvidia,num-lanes = <2>;
42 nvidia,num-lanes = <2>;
HDexynos5440.dtsi281 num-lanes = <4>;
302 num-lanes = <4>;
HDtegra30-cardhu.dtsi53 nvidia,num-lanes = <4>;
57 nvidia,num-lanes = <1>;
62 nvidia,num-lanes = <1>;
HDtegra30-apalis.dtsi22 nvidia,num-lanes = <4>;
26 nvidia,num-lanes = <1>;
30 nvidia,num-lanes = <1>;
HDk2e.dtsi100 num-lanes = <2>;
HDspear1340.dtsi58 num-lanes = <1>;
HDexynos4412-trats2.dts184 data-lanes = <1 2 3 4>;
818 data-lanes = <1 2 3 4>;
838 data-lanes = <1>;
878 data-lanes = <1>;
HDtegra30.dtsi60 nvidia,num-lanes = <2>;
73 nvidia,num-lanes = <2>;
86 nvidia,num-lanes = <2>;
HDomap4-sdp.dts638 lanes = <0 1 2 3 4 5>;
663 lanes = <0 1 2 3 4 5>;
HDkeystone.dtsi300 num-lanes = <2>;
HDarmada-xp-mv78230.dtsi86 * configured as x4 or quad x1 lanes. One unit is
HDtegra20.dtsi605 nvidia,num-lanes = <2>;
618 nvidia,num-lanes = <2>;
/NextBSD/sys/contrib/alpine-hal/
HDal_hal_pcie.h484 uint8_t lanes; member
590 int al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes);
HDal_hal_pcie.c1362 al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes) in al_pcie_port_max_lanes_set() argument
1373 uint32_t active_lanes_val = AL_PCIE_PARSE_LANES(lanes); in al_pcie_port_max_lanes_set()
1381 pcie_port->max_lanes = lanes; in al_pcie_port_max_lanes_set()
1943 status->lanes = 0; in al_pcie_link_status()
1964 status->lanes = (pcie_lnksta & AL_PCI_EXP_LNKSTA_NLW) >> AL_PCI_EXP_LNKSTA_NLW_SHIFT; in al_pcie_link_status()
1966 pcie_port->port_id, status->speed, status->lanes); in al_pcie_link_status()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64RegisterInfo.td474 class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind>
476 let Name = "TypedVectorList" # count # "_" # lanes # kind;
479 = "isTypedVectorList<" # count # ", " # lanes # ", '" # kind # "'>";
483 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string kind>
484 : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"
HDAArch64Schedule.td95 // Read the unwritten lanes of the VLD's destination registers.
HDAArch64CallingConvention.td30 // their lanes are in a consistent order.
90 // their lanes are in a consistent order.
/NextBSD/contrib/llvm/tools/clang/include/clang/Basic/
HDarm_neon.td78 // - "H" - Halve the number of lanes in the type.
79 // - "D" - Double the number of lanes in the type.
94 // all lanes. The type of the vector is the base type of the intrinsic.
159 // is a width in bits to reverse. The lanes this maps to is determined
164 // mask0 - The initial sequence of lanes for shuffle ARG0
166 // mask0 - The initial sequence of lanes for shuffle ARG1
645 // E.3.16 Extract lanes from a vector
651 // E.3.17 Set lanes within a vector
663 // E.3.19 Set all lanes to same value
1081 // Set all lanes to same value
/NextBSD/sys/dev/drm2/radeon/
HDradeon_asic.h173 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
353 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
HDrv770.c1224 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
1257 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
1260 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()

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