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Searched refs:mfspr (Results 1 – 25 of 34) sorted by relevance

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/NextBSD/sys/powerpc/aim/
HDmp_cpudep.c127 ccr = mfspr(SPR_L2CR); in mpc74xx_l2_enable()
135 ccr = mfspr(SPR_L2CR); in mpc74xx_l2_enable()
149 ccr = mfspr(SPR_L3CR); in mpc745x_l3_enable()
161 while (mfspr(SPR_L3CR) & L3CR_L3I) in mpc745x_l3_enable()
181 hid = mfspr(SPR_HID0); in mpc74xx_l1d_enable()
199 hid = mfspr(SPR_HID0); in mpc74xx_l1i_enable()
224 bsp_state[0] = mfspr(SPR_HID0); in cpudep_save_config()
225 bsp_state[1] = mfspr(SPR_HID1); in cpudep_save_config()
226 bsp_state[2] = mfspr(SPR_HID4); in cpudep_save_config()
227 bsp_state[3] = mfspr(SPR_HID5); in cpudep_save_config()
[all …]
HDaim_machdep.c204 scratch = mfspr(SPR_HID5); in aim_cpu_init()
474 msscr0 = mfspr(SPR_MSSCR0); in flush_disable_caches()
487 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); in flush_disable_caches()
518 cache_reg = mfspr(SPR_L2CR); in flush_disable_caches()
524 while (mfspr(SPR_L2CR) & L2CR_L2HWF) in flush_disable_caches()
532 while (mfspr(SPR_L2CR) & L2CR_L2I) in flush_disable_caches()
537 cache_reg = mfspr(SPR_L3CR); in flush_disable_caches()
543 while (mfspr(SPR_L3CR) & L3CR_L3HWF) in flush_disable_caches()
551 while (mfspr(SPR_L3CR) & L3CR_L3I) in flush_disable_caches()
556 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE); in flush_disable_caches()
[all …]
HDtrap_subr32.S400 mfspr %r2, SPR_HASH1 /* get first pointer */
403 mfspr %r3, SPR_ICMP /* get first compare value */
418 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */
419 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
431 mfspr %r2, SPR_HASH2 /* get the second pointer */
439 mfspr %r3, SPR_SRR1 /* get srr1 */
445 mfspr %r3, SPR_SRR1 /* get srr1 */
465 mfspr %r2, SPR_HASH1 /* get first pointer */
468 mfspr %r3, SPR_DCMP /* get first compare value */
481 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
[all …]
/NextBSD/sys/powerpc/booke/
HDmachdep_e500.c65 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
71 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
77 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
83 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
97 csr = mfspr(SPR_L2CSR0); in booke_enable_l2_cache()
103 csr = mfspr(SPR_L2CSR0); in booke_enable_l2_cache()
116 csr = mfspr(SPR_BUCSR); in booke_enable_bpred()
HDlocore.S505 mfspr %r17, SPR_PID0
510 mfspr %r17, SPR_MAS0
514 mfspr %r17, SPR_MAS1
564 mfspr %r5, SPR_MAS1
590 mfspr %r3, SPR_TLB1CFG /* Get number of entries */
598 mfspr %r5, SPR_MAS1
666 mfspr %r3, SPR_L1CSR0
672 1: mfspr %r3, SPR_L1CSR0
679 mfspr %r3, SPR_L1CSR0
691 mfspr %r3, SPR_L1CSR0
[all …]
HDtrap_subr.S123 mfspr %r30, isrr0; \
124 mfspr %r31, isrr1; /* MSR at interrupt time */ \
128 mfspr %r1, sprg_sp; /* Restore SP */ \
146 mfspr %r30, isrr0; \
147 mfspr %r31, isrr1; /* MSR at interrupt time */ \
150 mfspr %r30, SPR_SRR0; \
151 mfspr %r31, SPR_SRR1; /* MSR at interrupt time */ \
155 mfspr %r1, sprg_sp; /* Restore SP */ \
189 mfspr %r31, sprg_sp; /* get saved SP */ \
216 mfspr %r3, SPR_DBCR0; \
[all …]
HDmp_cpudep.c56 csr = mfspr(SPR_L1CSR0); in cpudep_ap_bootstrap()
62 csr = mfspr(SPR_L1CSR1); in cpudep_ap_bootstrap()
HDpmap.c494 tlb0_cfg = mfspr(SPR_TLB0CFG); in tlb0_get_tlbconf()
506 tlb1_cfg = mfspr(SPR_TLB1CFG); in tlb1_get_tlbconf()
2007 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); in mmu_booke_deactivate()
3028 mas1 = mfspr(SPR_MAS1); in tlb0_print_tlbentries()
3029 mas2 = mfspr(SPR_MAS2); in tlb0_print_tlbentries()
3030 mas3 = mfspr(SPR_MAS3); in tlb0_print_tlbentries()
3031 mas7 = mfspr(SPR_MAS7); in tlb0_print_tlbentries()
3264 mas1 = mfspr(SPR_MAS1); in tlb1_init()
3265 mas2 = mfspr(SPR_MAS2); in tlb1_init()
3266 mas3 = mfspr(SPR_MAS3); in tlb1_init()
[all …]
HDbooke_machdep.c397 r = mfspr(SPR_DBCR0); in kdb_cpu_clear_singlestep()
407 r = mfspr(SPR_DBCR0); in kdb_cpu_set_singlestep()
HDmachdep_ppc4xx.c128 ccr1 = mfspr(SPR_CCR1); in booke_disable_l2_cache()
/NextBSD/sys/dev/hwpmc/
HDhwpmc_mpc7xxx.c322 return mfspr(SPR_PMC1); in mpc7xxx_pmcn_read()
325 return mfspr(SPR_PMC2); in mpc7xxx_pmcn_read()
328 return mfspr(SPR_PMC3); in mpc7xxx_pmcn_read()
331 return mfspr(SPR_PMC4); in mpc7xxx_pmcn_read()
334 return mfspr(SPR_PMC5); in mpc7xxx_pmcn_read()
337 return mfspr(SPR_PMC6); in mpc7xxx_pmcn_read()
456 pmc_mmcr = mfspr(SPR_MMCR0); in mpc7xxx_start_pmc()
461 pmc_mmcr = mfspr(SPR_MMCR0); in mpc7xxx_start_pmc()
466 pmc_mmcr = mfspr(SPR_MMCR1); in mpc7xxx_start_pmc()
471 pmc_mmcr = mfspr(SPR_MMCR0); in mpc7xxx_start_pmc()
[all …]
HDhwpmc_ppc970.c277 val = mfspr(SPR_970PMC1); in ppc970_pmcn_read()
280 val = mfspr(SPR_970PMC2); in ppc970_pmcn_read()
283 val = mfspr(SPR_970PMC3); in ppc970_pmcn_read()
286 val = mfspr(SPR_970PMC4); in ppc970_pmcn_read()
289 val = mfspr(SPR_970PMC5); in ppc970_pmcn_read()
292 val = mfspr(SPR_970PMC6); in ppc970_pmcn_read()
295 val = mfspr(SPR_970PMC7); in ppc970_pmcn_read()
298 val = mfspr(SPR_970PMC8); in ppc970_pmcn_read()
379 pmc_mmcr = mfspr(SPR_970MMCR0); in ppc970_set_pmc()
389 pmc_mmcr = mfspr(SPR_970MMCR1); in ppc970_set_pmc()
[all …]
/NextBSD/sys/powerpc/powerpc/
HDcpu.c323 *cps = (mfspr(SPR_PMC1) * 1000) + 4999; in cpu_est_clockrate()
343 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999; in cpu_est_clockrate()
389 hid0 = mfspr(SPR_HID0); in cpu_6xx_setup()
480 hid = mfspr(SPR_HID0); in cpu_6xx_print_cacheinfo()
486 if (mfspr(SPR_L2CR) & L2CR_L2E) { in cpu_6xx_print_cacheinfo()
492 if (mfspr(SPR_L3CR) & L3CR_L3E) in cpu_6xx_print_cacheinfo()
494 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1'); in cpu_6xx_print_cacheinfo()
503 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) { in cpu_6xx_print_cacheinfo()
514 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT) in cpu_6xx_print_cacheinfo()
516 if (mfspr(SPR_L2CR) & L2CR_L2PE) in cpu_6xx_print_cacheinfo()
[all …]
HDclock.c247 tcr = mfspr(SPR_TCR); in decr_et_start()
277 tcr = mfspr(SPR_TCR); in decr_et_stop()
HDtrap.c282 mtspr(SPR_DBSR, mfspr(SPR_DBSR));
435 (u_long)mfspr(SPR_MSSSR0));
437 pa = mfspr(SPR_MCARU);
438 pa = (pa << 32) | mfspr(SPR_MCAR);
439 printf(" mcsr = 0x%lx\n", (u_long)mfspr(SPR_MCSR));
HDmp_machdep.c76 PCPU_SET(pir, mfspr(SPR_PIR)); in machdep_ap_bootstrap()
229 PCPU_SET(pir, mfspr(SPR_PIR)); in cpu_mp_unleash()
/NextBSD/sys/powerpc/mpc85xx/
HDmpc85xx.c85 ver = SVR_VER(mfspr(SPR_SVR)); in law_getmax()
221 ver = SVR_VER(mfspr(SPR_SVR)); in law_pci_target()
288 ver = SVR_VER(mfspr(SPR_SVR)); in mpc85xx_enable_l3_cache()
311 uint32_t svr = SVR_VER(mfspr(SPR_SVR)); in mpc85xx_dataloss_erratum_spr976()
322 mtspr(976, (mfspr(976) & ~0x1f8) | 0x48); in mpc85xx_dataloss_erratum_spr976()
365 uint32_t svr = SVR_VER(mfspr(SPR_SVR)); in mpc85xx_fix_errata()
HDplatform_mpc85xx.c314 cpuref->cr_cpuid = mfspr(SPR_PIR); in mpc85xx_smp_get_bsp()
362 tlb1[0] = mfspr(SPR_MAS1); in mpc85xx_smp_start_cpu()
363 tlb1[1] = mfspr(SPR_MAS2); in mpc85xx_smp_start_cpu()
364 tlb1[2] = mfspr(SPR_MAS3); in mpc85xx_smp_start_cpu()
478 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); in mpc85xx_reset()
HDmpc85xx_gpio.c201 svr = mfspr(SPR_SVR); in mpc85xx_gpio_probe()
/NextBSD/sys/powerpc/include/
HDcpufunc.h148 *tbup = mfspr(TBR_TBU); in mftb()
149 *tblp = mfspr(TBR_TBL); in mftb()
150 } while (*tbup != mfspr(TBR_TBU)); in mftb()
/NextBSD/sys/powerpc/cpufreq/
HDdfs.c173 hid1 = mfspr(SPR_HID1); in dfs_set()
205 hid1 = mfspr(SPR_HID1); in dfs_get()
HDpcr.c147 (void)mfspr(SPR_SCOMC); /* Complete transcation */ in read_scom()
/NextBSD/sys/boot/powerpc/ps3/
HDstart.S96 mfspr %r3,SPR_CTRL
/NextBSD/crypto/openssl/crypto/perlasm/
HDppc-xlate.pl165 my $mfspr = sub {
/NextBSD/contrib/gcc/config/rs6000/
HDdarwin-vecsave.asm132 mfspr r11,VRsave

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