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Searched refs:mtspr (Results 1 – 25 of 26) sorted by relevance

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/NextBSD/sys/powerpc/aim/
HDmp_cpudep.c75 mtspr(SPR_HID4, bsp_state[2]); powerpc_sync(); isync(); in cpudep_ap_early_bootstrap()
76 mtspr(SPR_HID5, bsp_state[3]); powerpc_sync(); isync(); in cpudep_ap_early_bootstrap()
133 mtspr(SPR_L2CR, ccr | L2CR_L2I); in mpc74xx_l2_enable()
138 mtspr(SPR_L2CR, l2cr_config); in mpc74xx_l2_enable()
155 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
157 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
159 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
160 mtspr(SPR_L3CR, ccr | L3CR_L3I); in mpc745x_l3_enable()
163 mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN); in mpc745x_l3_enable()
166 mtspr(SPR_L3CR, ccr); in mpc745x_l3_enable()
[all …]
HDaim_machdep.c206 mtspr(SPR_HID5, scratch); in aim_cpu_init()
476 mtspr(SPR_MSSCR0, msscr0); in flush_disable_caches()
487 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); in flush_disable_caches()
491 mtspr(SPR_LDSTCR, 0); in flush_disable_caches()
508 mtspr(SPR_LDSTCR, x); in flush_disable_caches()
516 mtspr(SPR_LDSTCR, 0); in flush_disable_caches()
521 mtspr(SPR_L2CR, cache_reg); in flush_disable_caches()
523 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); in flush_disable_caches()
528 mtspr(SPR_L2CR, cache_reg); in flush_disable_caches()
530 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); in flush_disable_caches()
[all …]
HDtrap_subr32.S421 mtspr SPR_RPA, %r1 /* set the pte */
451 mtspr SPR_SRR1, %r2 /* set srr1 */
484 mtspr SPR_RPA, %r1 /* set the pte */
530 mtspr SPR_RPA, %r1 /* set the pte */
580 mtspr SPR_SRR1, %r2 /* set srr1 */
581 mtspr SPR_DSISR, %r1 /* load the dsisr */
587 mtspr SPR_DAR, %r1 /* put in dar */
HDmmu_oea64.c568 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); in moea64_probe_large_page()
/NextBSD/sys/powerpc/booke/
HDlocore.S128 mtspr SPR_HID0, %r4
142 mtspr SPR_HID1, %r3
172 mtspr SPR_SRR0, %r4
173 mtspr SPR_SRR1, %r3
189 mtspr SPR_MAS0, %r3
194 mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */
202 mtspr SPR_MAS2, %r3
210 mtspr SPR_MAS3, %r4 /* Set RPN and protection */
226 mtspr SPR_SRR0, %r4
227 mtspr SPR_SRR1, %r3
[all …]
HDtrap_subr.S115 mtspr sprg_sp, %r1; /* Save SP */ \
138 mtspr sprg_sp, %r1; /* Save SP */ \
245 mtspr SPR_DBCR0, %r4; \
249 mtspr isrr0, %r30; \
250 mtspr isrr1, %r31; \
630 mtspr SPR_MAS0, %r29
632 mtspr SPR_MAS1, %r28
634 mtspr SPR_MAS2, %r27
636 mtspr SPR_MAS3, %r23
740 mtspr SPR_MAS0, %r29
[all …]
HDbooke_machdep.c205 mtspr(ivor, (uintptr_t)(&handler) & 0xffffUL);
223 mtspr(SPR_IVPR, ((uintptr_t)&interrupt_vector_base) & 0xffff0000); in ivor_setup()
398 mtspr(SPR_DBCR0, r & ~DBCR0_IC); in kdb_cpu_clear_singlestep()
408 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM); in kdb_cpu_set_singlestep()
HDpmap.c1983 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); in mmu_booke_activate()
1986 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); in mmu_booke_activate()
3020 mtspr(SPR_MAS0, mas0); in tlb0_print_tlbentries()
3024 mtspr(SPR_MAS2, mas2); in tlb0_print_tlbentries()
3065 mtspr(SPR_MAS0, mas0); in tlb1_write_entry()
3067 mtspr(SPR_MAS1, tlb1[idx].mas1); in tlb1_write_entry()
3069 mtspr(SPR_MAS2, tlb1[idx].mas2); in tlb1_write_entry()
3071 mtspr(SPR_MAS3, tlb1[idx].mas3); in tlb1_write_entry()
3076 mtspr(SPR_MAS8, 0); in tlb1_write_entry()
3080 mtspr(SPR_MAS7, tlb1[idx].mas7); in tlb1_write_entry()
[all …]
HDmachdep_ppc4xx.c130 mtspr(SPR_CCR1, ccr1); in booke_disable_l2_cache()
/NextBSD/sys/dev/hwpmc/
HDhwpmc_mpc7xxx.c348 mtspr(SPR_PMC1, val); in mpc7xxx_pmcn_write()
351 mtspr(SPR_PMC2, val); in mpc7xxx_pmcn_write()
354 mtspr(SPR_PMC3, val); in mpc7xxx_pmcn_write()
357 mtspr(SPR_PMC4, val); in mpc7xxx_pmcn_write()
360 mtspr(SPR_PMC5, val); in mpc7xxx_pmcn_write()
363 mtspr(SPR_PMC6, val); in mpc7xxx_pmcn_write()
458 mtspr(SPR_MMCR0, pmc_mmcr); in mpc7xxx_start_pmc()
463 mtspr(SPR_MMCR0, pmc_mmcr); in mpc7xxx_start_pmc()
468 mtspr(SPR_MMCR1, pmc_mmcr); in mpc7xxx_start_pmc()
473 mtspr(SPR_MMCR0, pmc_mmcr); in mpc7xxx_start_pmc()
[all …]
HDhwpmc_ppc970.c312 mtspr(SPR_970PMC1, val); in ppc970_pmcn_write()
315 mtspr(SPR_970PMC2, val); in ppc970_pmcn_write()
318 mtspr(SPR_970PMC3, val); in ppc970_pmcn_write()
321 mtspr(SPR_970PMC4, val); in ppc970_pmcn_write()
324 mtspr(SPR_970PMC5, val); in ppc970_pmcn_write()
327 mtspr(SPR_970PMC6, val); in ppc970_pmcn_write()
330 mtspr(SPR_970PMC7, val); in ppc970_pmcn_write()
333 mtspr(SPR_970PMC8, val); in ppc970_pmcn_write()
381 mtspr(SPR_970MMCR0, pmc_mmcr); in ppc970_set_pmc()
391 mtspr(SPR_970MMCR1, pmc_mmcr); in ppc970_set_pmc()
[all …]
/NextBSD/sys/powerpc/powerpc/
HDcpu.c319 mtspr(SPR_MMCR0, SPR_MMCR0_FC); in cpu_est_clockrate()
320 mtspr(SPR_PMC1, 0); in cpu_est_clockrate()
321 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); in cpu_est_clockrate()
324 mtspr(SPR_MMCR0, SPR_MMCR0_FC); in cpu_est_clockrate()
332 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); in cpu_est_clockrate()
334 mtspr(SPR_970MMCR1, 0); in cpu_est_clockrate()
335 mtspr(SPR_970MMCRA, 0); in cpu_est_clockrate()
336 mtspr(SPR_970PMC1, 0); in cpu_est_clockrate()
337 mtspr(SPR_970MMCR0, in cpu_est_clockrate()
342 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); in cpu_est_clockrate()
[all …]
HDclock.c127 mtspr(SPR_TSR, TSR_DIS); in decr_intr()
250 mtspr(SPR_DECAR, s->div); in decr_et_start()
255 mtspr(SPR_TCR, tcr); in decr_et_start()
279 mtspr(SPR_TCR, tcr); in decr_et_stop()
HDtrap.c282 mtspr(SPR_DBSR, mfspr(SPR_DBSR));
/NextBSD/sys/powerpc/include/
HDcpufunc.h160 mtspr(TBR_TBWL, 0); in mttb()
161 mtspr(TBR_TBWU, (uint32_t)(time >> 32)); in mttb()
162 mtspr(TBR_TBWL, (uint32_t)(time & 0xffffffff)); in mttb()
HDspr.h33 #define mtspr(reg, val) \ macro
/NextBSD/sys/powerpc/cpufreq/
HDpcr.c119 mtspr(SPR_SCOMD, value); in write_scom()
126 mtspr(SPR_SCOMC, address | SCOMC_WRITE); in write_scom()
141 mtspr(SPR_SCOMC, address | SCOMC_READ); in read_scom()
HDdfs.c187 mtspr(SPR_HID1, hid1); in dfs_set()
/NextBSD/sys/powerpc/mpc85xx/
HDplatform_mpc85xx.c360 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i)); in mpc85xx_smp_start_cpu()
471 mtspr(SPR_DBCR0, 0); in mpc85xx_reset()
478 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); in mpc85xx_reset()
HDmpc85xx.c322 mtspr(976, (mfspr(976) & ~0x1f8) | 0x48); in mpc85xx_dataloss_erratum_spr976()
/NextBSD/crypto/openssl/crypto/perlasm/
HDppc-xlate.pl157 my $mtspr = sub {
/NextBSD/contrib/gcc/config/rs6000/
HDdarwin-vecsave.asm164 mtspr VRsave,r10
HDdarwin-world.asm221 mtspr VRsave,r0
HDaltivec.md272 return "mtspr 256,%1";
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstr64Bit.td336 "mtspr $SPR, $RT", IIC_SprMTSPR>;

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