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Searched refs:outb (Results 1 – 25 of 127) sorted by relevance

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/NextBSD/sys/pc98/pc98/
HDpc98_machdep.c61 outb(0x439, (inb(0x439) & 0xfb)); /* DMA Accsess Control over 1MB */ in pc98_init_dmac()
62 outb(0x29, (0x0c | 0)); /* Bank Mode Reg. 16M mode */ in pc98_init_dmac()
63 outb(0x29, (0x0c | 1)); /* Bank Mode Reg. 16M mode */ in pc98_init_dmac()
64 outb(0x29, (0x0c | 2)); /* Bank Mode Reg. 16M mode */ in pc98_init_dmac()
65 outb(0x29, (0x0c | 3)); /* Bank Mode Reg. 16M mode */ in pc98_init_dmac()
66 outb(0x11, 0x50); in pc98_init_dmac()
85 outb(0x43f, 0x42); in init_epson_memwin()
89 outb(0xc48, 0x49); in init_epson_memwin()
90 outb(0xc4c, 0x00); in init_epson_memwin()
91 outb(0xc48, 0x48); in init_epson_memwin()
[all …]
/NextBSD/sys/dev/ctau/
HDctau.c91 outb (BCR1(port), cr1); in ct_download()
93 outb (BCR0(port), BCR0_TCK); in ct_download()
94 outb (BCR0(port), 0); in ct_download()
144 #define nconfig_set(b) outb (bcr1_port, (bcr1 &= ~BCR1_NCONFIGI))
145 #define nconfig_clr(b) outb (bcr1_port, (bcr1 |= BCR1_NCONFIGI))
147 #define dclk_tick(b) outb (BCR3(b), 0)
151 outb (bcr1_port, bcr1); \
265 outb (BCR0(port), 0); in ct_probe2_board()
301 outb (BCR0(port), 0); in ct_probe_board()
316 outb (0x20, 0x0a); in ct_probe_irq()
[all …]
/NextBSD/sys/dev/ppc/
HDppc.c450 outb(idport, PC873_SID); in ppc_pc873xx_detect()
472 outb(idport, pc873xx_regstab[i]); in ppc_pc873xx_detect()
482 outb(idport, PC873_FER); in ppc_pc873xx_detect()
489 outb(idport, PC873_FAR); in ppc_pc873xx_detect()
514 outb(idport, PC873_FAR); in ppc_pc873xx_detect()
515 outb(idport + 1, val); in ppc_pc873xx_detect()
516 outb(idport + 1, val); in ppc_pc873xx_detect()
521 outb(idport, PC873_FAR); in ppc_pc873xx_detect()
534 outb(idport, PC873_PTR); in ppc_pc873xx_detect()
556 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); in ppc_pc873xx_detect()
[all …]
/NextBSD/sys/x86/isa/
HDisa_dma.c219 outb(DMA1_MODE, DMA37MD_CASCADE | chan);
220 outb(DMA1_SMSK, chan);
222 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
223 outb(DMA2_SMSK, chan & 3);
301 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); in isa_dmastart()
303 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); in isa_dmastart()
307 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); in isa_dmastart()
309 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); in isa_dmastart()
310 outb(DMA1_FFC, 0); in isa_dmastart()
314 outb(waport, phys); in isa_dmastart()
[all …]
HDclock.c175 outb(0x61, inb(0x61) | 0x80); in clkintr()
203 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); in timer_spkr_acquire()
205 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); in timer_spkr_acquire()
219 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); in timer_spkr_release()
221 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); in timer_spkr_release()
234 outb(TIMER_CNTR1, freq & 0xff); in timer_spkr_setfreq()
235 outb(TIMER_CNTR1, freq >> 8); in timer_spkr_setfreq()
237 outb(TIMER_CNTR2, freq & 0xff); in timer_spkr_setfreq()
238 outb(TIMER_CNTR2, freq >> 8); in timer_spkr_setfreq()
251 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); in getit()
[all …]
HDatpic.c167 outb(atpics[MASTER].at_ioaddr, OCW2_EOI); in _atpic_eoi_master()
182 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI); in _atpic_eoi_slave()
184 outb(atpics[MASTER].at_ioaddr, OCW2_EOI); in _atpic_eoi_slave()
198 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen); in atpic_enable_source()
212 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen); in atpic_disable_source()
380 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM); in i8259_init()
383 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4); in i8259_init()
387 outb(imr_addr, pic->at_intbase); in i8259_init()
395 outb(imr_addr, ICU_SLAVEID); in i8259_init()
397 outb(imr_addr, IRQ_MASK(ICU_SLAVEID)); in i8259_init()
[all …]
/NextBSD/lib/libvgl/
HDsimple.c123 outb(0x3c4, 0x02); in VGLSetXY()
124 outb(0x3c5, 0x01 << (x&0x3)); in VGLSetXY()
133 outb(0x3c4, 0x02); outb(0x3c5, 0x0f); in VGLSetXY()
134 outb(0x3ce, 0x00); outb(0x3cf, (byte)color & 0x0f); /* set/reset */ in VGLSetXY()
135 outb(0x3ce, 0x01); outb(0x3cf, 0x0f); /* set/reset enable */ in VGLSetXY()
136 outb(0x3ce, 0x08); outb(0x3cf, 0x80 >> (x%8)); /* bit mask */ in VGLSetXY()
178 outb(0x3ce, 0x04); outb(0x3cf, x & 0x3); in VGLGetXY()
192 outb(0x3ce, 0x04); outb(0x3cf, i); in VGLGetXY()
548 outb(0x3c6, 0xff); in VGLClear()
549 outb(0x3c4, 0x02); outb(0x3c5, 0x0f); in VGLClear()
[all …]
HDmain.c413 outb(0x3c6, 0xff); in VGLCheckSwitch()
414 outb(0x3ce, 0x01); outb(0x3cf, 0x00); /* set/reset enable */ in VGLCheckSwitch()
415 outb(0x3ce, 0x08); outb(0x3cf, 0xff); /* bit mask */ in VGLCheckSwitch()
422 outb(0x3c4, 0x02); in VGLCheckSwitch()
423 outb(0x3c5, 0x01<<i); in VGLCheckSwitch()
431 outb(0x3c6, 0xff); in VGLCheckSwitch()
432 outb(0x3ce, 0x01); outb(0x3cf, 0x00); /* set/reset enable */ in VGLCheckSwitch()
433 outb(0x3ce, 0x08); outb(0x3cf, 0xff); /* bit mask */ in VGLCheckSwitch()
435 outb(0x3c4, 0x02); in VGLCheckSwitch()
436 outb(0x3c5, 0x01<<i); in VGLCheckSwitch()
[all …]
HDbitmap.c91 outb(0x3ce, 0x01); outb(0x3cf, 0x00); /* set/reset enable */ in WriteVerticalLine()
92 outb(0x3ce, 0x08); outb(0x3cf, 0xff); /* bit mask */ in WriteVerticalLine()
94 outb(0x3c4, 0x02); in WriteVerticalLine()
95 outb(0x3c5, 0x01<<i); in WriteVerticalLine()
96 outb(0x3ce, 0x04); in WriteVerticalLine()
97 outb(0x3cf, i); in WriteVerticalLine()
128 outb(0x3c4, 0x02); in WriteVerticalLine()
129 outb(0x3c5, 0x01 << ((x + i)%4)); in WriteVerticalLine()
197 outb(0x3ce, 0x04); in ReadVerticalLine()
198 outb(0x3cf, i); in ReadVerticalLine()
[all …]
/NextBSD/sys/dev/fb/
HDvga.c804 outb(adp->va_crtc_addr, 7); in verify_adapter()
1072 outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr, 12); in probe_adapters()
1073 outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr + 1, 0); in probe_adapters()
1074 outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr, 13); in probe_adapters()
1075 outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr + 1, 0); in probe_adapters()
1267 outb(adp->va_crtc_addr, 0x13); in set_line_length()
1268 outb(adp->va_crtc_addr + 1, count); in set_line_length()
1291 outb(TSIDX, 1); in set_display_start()
1309 outb(adp->va_crtc_addr, 0xc); /* high */ in set_display_start()
1310 outb(adp->va_crtc_addr + 1, off >> 8); in set_display_start()
[all …]
/NextBSD/sys/dev/cx/
HDcsigma.c82 outb (port, cmd); in cx_cmd()
129 outb (BCR2(port), cr2); in cx_download()
131 outb (BCR0(port), BCR0800_TCK); in cx_download()
132 outb (BCR0(port), 0); in cx_download()
207 outb (BCR0(port), 0); in cx_probe_800_chained_board()
208 outb (BCR1(port), 0); in cx_probe_800_chained_board()
209 outb (BCR2(port), 0); in cx_probe_800_chained_board()
280 outb (BCR0(port), BCR0_NORESET); in cx_probe_board()
282 outb (BCR0(port + 0x10), BCR0_NORESET); in cx_probe_board()
296 outb (BCR0(port), 0); in cx_probe_board()
[all …]
HDcxddk.c102 outb (BCR0(b->port), 0); in cx_close_board()
104 outb (BCR0(b->port+0x10), 0); in cx_close_board()
132 outb (CAR(c->port), c->num & 3); in cx_start_chan()
166 outb (CMR(c->port), mode | (c->mode == M_ASYNC ? CMR_ASYNC : CMR_HDLC)); in cx_start_chan()
185 outb (IER(c->port), ier); in cx_start_chan()
200 outb (CAR(c->port), c->num & 3); in cx_enable_receive()
203 outb (IER(c->port), ier & ~ (IER_RXD | IER_RET)); in cx_enable_receive()
207 outb (CAR(c->port), c->num & 3); in cx_enable_receive()
210 outb (IER(c->port), ier | (IER_RXD | IER_RET)); in cx_enable_receive()
212 outb (IER(c->port), ier | IER_RXD); in cx_enable_receive()
[all …]
HDmachdep.h29 # define outb(port,b) outportb(port,b) macro
41 # define outb(port,b) outp((unsigned short)(port),b) macro
58 { outb (byte, port); } in __ddk_outb()
61 # undef outb
63 # define outb(port,val) __ddk_outb(port, val) macro
/NextBSD/sys/pc98/cbus/
HDsio.c876 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2);
878 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0);
887 outb(xioport + com_mcr, 0);
919 outb(iod.cmd, 0);
921 outb(iod.cmd, 0);
923 outb(iod.cmd, 0);
925 outb(iod.cmd, CMD8251_RESET);
927 outb(iod.cmd, 0xf2); /* MODE (dummy) */
929 outb(iod.cmd, 0x01); /* CMD (dummy) */
937 outb( iod.ctrl, tmp|IEN_TxEMP );
[all …]
HDpcrtc.c57 outb(IO_RTC, ((i&0x01)<<5)|0x07); in rtc_serialcombit()
59 outb(IO_RTC, ((i&0x01)<<5)|0x17); in rtc_serialcombit()
61 outb(IO_RTC, ((i&0x01)<<5)|0x07); in rtc_serialcombit()
72 outb(IO_RTC, 0x07); in rtc_serialcom()
74 outb(IO_RTC, 0x0f); in rtc_serialcom()
76 outb(IO_RTC, 0x07); in rtc_serialcom()
88 outb(IO_RTC, sa); /* set DI & CLK 0 */ in rtc_outb()
90 outb(IO_RTC, sa | 0x10); /* CLK 1 */ in rtc_outb()
93 outb(IO_RTC, sa & 0xef); /* CLK 0 */ in rtc_outb()
104 outb(IO_RTC, 0x17); /* CLK 1 */ in rtc_inb()
[all …]
HDcbus_dma.c257 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); in isa_dmastart()
259 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); in isa_dmastart()
262 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); in isa_dmastart()
264 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); in isa_dmastart()
266 outb(DMA1_FFC, 0); in isa_dmastart()
270 outb(waport, phys); in isa_dmastart()
271 outb(waport, phys>>8); in isa_dmastart()
272 outb(dmapageport[chan], phys>>16); in isa_dmastart()
275 outb(waport + 2, --nbytes); in isa_dmastart()
276 outb(waport + 2, nbytes>>8); in isa_dmastart()
[all …]
HDgdc.c673 outb(TEXT_GDC+2, cmd); in master_gdc_cmd()
679 outb(TEXT_GDC, pmtr); in master_gdc_prm()
704 outb( GRAPHIC_GDC+2, cmd); in gdc_cmd()
711 outb( GRAPHIC_GDC, pmtr); in gdc_prm()
760 outb(0x9a8, (hsync_clock == _31KHZ) ? 1 : 0); in initialize_gdc()
770 outb(0x6a, 0x83); in initialize_gdc()
771 outb(0x6a, 0x85); in initialize_gdc()
889 outb(0xa8, i); in gdc_load_palette()
890 outb(0xac, *palette++); /* R */ in gdc_load_palette()
891 outb(0xaa, *palette++); /* G */ in gdc_load_palette()
[all …]
/NextBSD/sys/boot/common/
HDisapnp.c41 #define outb(x,y) (archsw.arch_isaoutb((x),(y))) macro
63 outb (_PNP_ADDRESS, d); in isapnp_write()
64 outb (_PNP_WRITE_DATA, r); in isapnp_write()
77 outb(_PNP_ADDRESS, 0); in isapnp_send_Initiation_LFSR()
78 outb(_PNP_ADDRESS, 0); /* yes, we do need it twice! */ in isapnp_send_Initiation_LFSR()
81 outb(_PNP_ADDRESS, cur); in isapnp_send_Initiation_LFSR()
85 outb(_PNP_ADDRESS, cur); in isapnp_send_Initiation_LFSR()
98 outb(_PNP_ADDRESS, SERIAL_ISOLATION); in isapnp_get_serial()
132 outb(_PNP_ADDRESS, STATUS); in isapnp_get_resource_info()
142 outb(_PNP_ADDRESS, RESOURCE_DATA); in isapnp_get_resource_info()
[all …]
/NextBSD/contrib/gdb/gdb/
HDser-go32.c242 #define outb(p,a,v) outportb((p)->base + (a), (v)) macro
492 outb (port, com_cfcr, 0); in dos_open()
493 outb (port, com_iir, 0); in dos_open()
505 outb (port, com_ier, 0); in dos_open()
508 outb (port, com_fifo, in dos_open()
518 outb (port, com_mcr, MCR_IENABLE); in dos_open()
524 outb (port, com_mcr, 0); in dos_open()
525 outb (port, com_fifo, 0); in dos_open()
543 outb (port, com_cfcr, CFCR_DLAB); in dos_open()
544 outb (port, com_dlbl, i & 0xff); in dos_open()
[all …]
/NextBSD/sys/dev/ie/
HDif_ie_isa.c121 outb(ELINK_ID_PORT, 0xff); in ie_isa_3C507_identify()
138 outb(port + IE507_CTRL, EL_CTRL_NRST); in ie_isa_3C507_identify()
199 outb(ELINK_ID_PORT, 0x00); in ie_isa_3C507_identify()
201 outb(ELINK_ID_PORT, 0x00); in ie_isa_3C507_identify()
257 outb(PORT(sc) + IE507_CTRL, EL_CTRL_NORMAL); in ie_isa_3C507_attach()
267 outb(PORT(sc) + IE507_ICTRL, 1); in ie_isa_3C507_attach()
348 outb(port + IEE16_ECTRL, IEE16_RESET_ASIC); in ie_isa_ee16_identify()
349 outb(port + IEE16_ECTRL, 0); in ie_isa_ee16_identify()
455 outb(PORT(sc) + IEE16_ECTRL, IEE16_RESET_ASIC); in ie_isa_ee16_attach()
456 outb(PORT(sc) + IEE16_ECTRL, 0); in ie_isa_ee16_attach()
[all …]
/NextBSD/sys/dev/mca/
HDmca_bus.c80 outb(MCA_MB_SETUP_REG, MCA_MB_SETUP_DIS); in mca_pos_set()
83 outb(MCA_ADAP_SETUP_REG, ((slot & 0x0f) | MCA_ADAP_SET)); in mca_pos_set()
86 outb(MCA_POS_REG(reg), data); in mca_pos_set()
89 outb(MCA_ADAP_SETUP_REG, MCA_ADAP_SETUP_DIS); in mca_pos_set()
107 outb(MCA_MB_SETUP_REG, MCA_MB_SETUP_DIS); in mca_pos_get()
113 outb(MCA_ADAP_SETUP_REG, MCA_ADAP_SETUP_DIS); in mca_pos_get()
116 outb(MCA_MB_SETUP_REG, MCA_MB_SETUP_SCSI); in mca_pos_get()
122 outb(MCA_MB_SETUP_REG, MCA_MB_SETUP_DIS); in mca_pos_get()
127 outb(MCA_ADAP_SETUP_REG, MCA_ADAP_SETUP_DIS); in mca_pos_get()
130 outb(MCA_MB_SETUP_REG, MCA_MB_SETUP_VIDEO); in mca_pos_get()
[all …]
/NextBSD/sys/dev/ep/
HDif_ep_isa.c128 outb(id_port, EEPROM_CMD_RD | offset); in get_eeprom_data()
173 outb(ELINK_ID_PORT, 0); in ep_isa_identify()
174 outb(ELINK_ID_PORT, 0); in ep_isa_identify()
182 outb(ELINK_ID_PORT, 0); in ep_isa_identify()
183 outb(ELINK_ID_PORT, 0); in ep_isa_identify()
192 outb(ELINK_ID_PORT, 0xd0); in ep_isa_identify()
194 outb(ELINK_ID_PORT, 0xd8); in ep_isa_identify()
241 outb(ELINK_ID_PORT, tag--); in ep_isa_identify()
259 outb(ELINK_ID_PORT, tag--); in ep_isa_identify()
264 outb(ELINK_ID_PORT, tag--); in ep_isa_identify()
[all …]
/NextBSD/sys/i386/xbox/
HDpic16l.s57 outb %al,%dx
60 outb %al,%dx
71 outb %al,%dx
141 outb %al,%dx
145 outb %al,%dx
149 outb %al,%dx
157 outb %al,%dx
/NextBSD/sys/x86/x86/
HDintr_machdep.c402 outb(IO_ICU1, ICW1_RESET | ICW1_IC4); in atpic_reset()
403 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS); in atpic_reset()
404 outb(IO_ICU1 + ICU_IMR_OFFSET, IRQ_MASK(ICU_SLAVEID)); in atpic_reset()
405 outb(IO_ICU1 + ICU_IMR_OFFSET, MASTER_MODE); in atpic_reset()
406 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff); in atpic_reset()
407 outb(IO_ICU1, OCW3_SEL | OCW3_RR); in atpic_reset()
409 outb(IO_ICU2, ICW1_RESET | ICW1_IC4); in atpic_reset()
410 outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8); in atpic_reset()
411 outb(IO_ICU2 + ICU_IMR_OFFSET, ICU_SLAVEID); in atpic_reset()
412 outb(IO_ICU2 + ICU_IMR_OFFSET, SLAVE_MODE); in atpic_reset()
[all …]
/NextBSD/sys/i386/isa/
HDelink.c58 outb(ELINK_ID_PORT, ELINK_RESET); in elink_reset()
60 outb(ELINK_ID_PORT, 0); in elink_reset()
61 outb(ELINK_ID_PORT, 0); in elink_reset()
78 outb(ELINK_ID_PORT, c); in elink_idseq()

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