Searched refs:pll_reg (Results 1 – 3 of 3) sorted by relevance
| /NextBSD/sys/mips/atheros/ |
| HD | ar71xxreg.h | 544 ar71xx_write_pll(uint32_t cfg_reg, uint32_t pll_reg, uint32_t pll, uint32_t pll_reg_shift) in ar71xx_write_pll() argument
556 ATH_WRITE_REG(pll_reg, pll); in ar71xx_write_pll()
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| /NextBSD/sys/dev/drm2/i915/ |
| HD | intel_display.c | 959 reg = intel_crtc->pch_pll->pll_reg; in assert_pch_pll()
1439 pll->pll_reg, pll->active, pll->on, in intel_enable_pch_pll()
1450 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); in intel_enable_pch_pll()
1452 reg = pll->pll_reg; in intel_enable_pch_pll()
1480 pll->pll_reg, pll->active, pll->on, in intel_disable_pch_pll()
1494 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); in intel_disable_pch_pll()
1499 reg = pll->pll_reg; in intel_disable_pch_pll()
2854 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) in ironlake_pch_enable()
2941 intel_crtc->base.base.id, pll->pll_reg); in intel_get_pch_pll()
2951 intel_crtc->base.base.id, pll->pll_reg); in intel_get_pch_pll()
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| HD | i915_drv.h | 88 int pll_reg; member
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