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Searched refs:v2i16 (Results 1 – 25 of 26) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrInfoVector.td18 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
40 defm : bitconvert_32<v2i16, i32>;
41 defm : bitconvert_32<v2i16, v4i8>;
75 def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
78 def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
274 def: Pat<(v2i16 (select I1:$Pu, V2I16:$Rs, V2I16:$Rt)),
345 def: Pat<(v2i16 (trunc V2I32:$Rs)),
366 // Sign extends a v2i16 into a v2i32.
367 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
371 // Multiplies two v2i16 and returns a v2i32. We are using here the
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HDHexagonISelLowering.cpp198 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) { in CC_Hexagon()
279 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) { in RetCC_Hexagon()
1022 if (LHSVT == MVT::v2i16) { in LowerSETCC()
1066 if (OpVT == MVT::v2i16) { in LowerVSELECT()
1070 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL); in LowerVSELECT()
1312 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1467 promoteLdStType(MVT::v2i16, MVT::i32); in HexagonTargetLowering()
1521 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32, in HexagonTargetLowering()
1538 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1539 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
[all …]
HDHexagonRegisterInfo.td166 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
178 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
204 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
215 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
218 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
232 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
235 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
246 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
249 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
HDAArch64ISelLowering.cpp586 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); in AArch64TargetLowering()
1752 case MVT::v2i16: in getExtensionTo64Bits()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsDSPInstrInfo.td1283 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1285 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1288 def : DSPPat<(v2i16 (load addr:$a)),
1289 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1292 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1302 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1303 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1304 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1305 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1306 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
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HDMipsSEISelLowering.cpp60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; in MipsSETargetLowering()
84 setOperationAction(ISD::MUL, MVT::v2i16, Legal); in MipsSETargetLowering()
878 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSHLCombine()
935 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2())) in performSRACombine()
947 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8)) in performSRLCombine()
954 bool IsV216 = (Ty == MVT::v2i16); in isLegalDSPCondCode()
974 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSETCCCombine()
1026 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { in performVSELECTCombine()
HDMipsRegisterInfo.td293 def DSPR : GPR32Class<[v4i8, v2i16]>;
436 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineValueType.h74 v2i16 = 27, // 2 x i16 enumerator
211 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || in is32BitVector()
299 case v2i16: in getVectorElementType()
363 case v2i16: in getVectorNumElements()
410 case v2i16: in getSizeInBits()
549 if (NumElements == 2) return MVT::v2i16; in getVectorVT()
HDValueTypes.td50 def v2i16 : ValueType<32 , 27>; // 2 x i16 vector value
/NextBSD/contrib/llvm/include/llvm/IR/
HDIntrinsicsNVVM.td1875 "llvm.nvvm.suld.1d.v2i16.clamp">;
1920 "llvm.nvvm.suld.1d.array.v2i16.clamp">;
1965 "llvm.nvvm.suld.2d.v2i16.clamp">;
2010 "llvm.nvvm.suld.2d.array.v2i16.clamp">;
2055 "llvm.nvvm.suld.3d.v2i16.clamp">;
2101 "llvm.nvvm.suld.1d.v2i16.trap">;
2146 "llvm.nvvm.suld.1d.array.v2i16.trap">;
2191 "llvm.nvvm.suld.2d.v2i16.trap">;
2236 "llvm.nvvm.suld.2d.array.v2i16.trap">;
2281 "llvm.nvvm.suld.3d.v2i16.trap">;
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HDIntrinsics.td172 def llvm_v2i16_ty : LLVMType<v2i16>; // 2 x i16
HDIntrinsicsMips.td16 def mips_v2q15_ty: LLVMType<v2i16>;
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
111 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
142 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
143 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
HDARMInstrNEON.td6737 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6741 // v2i8 -> v2i16 -> v2i32
6743 // v2i16 -> v2i32 -> v2i64
6749 defm : Lengthen_HalfSingle_Big_Endian<"2", "i32", "i16", "4", "i32", "16">; // v2i16 -> v2i32
6753 // v2i8 -> v2i16 -> v2i32
6755 // v2i16 -> v2i32 -> v2i64
6759 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
HDARMISelLowering.cpp593 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16, in ARMTargetLowering()
6043 case MVT::v2i16: in getExtensionTo64Bits()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXVector.td25 // Extract v2i16
30 (v2i16 V2I16Regs:$src), imm:$c))],
125 // Insert v2i16
790 def : Pat<(v2i16 (vec_shuf:$op V2I16Regs:$src1, V2I16Regs:$src2)),
884 def : Pat<(v2i16 (extract_subvec V4I16Regs:$src, 0)),
887 def : Pat<(v2i16 (extract_subvec V4I16Regs:$src, 2)),
1268 // v2i16 -> i32
1294 // i32 -> v2i16
1307 // v4i8 -> v2i16
1308 def : Pat<(v2i16 (bitconvert V4I8Regs:$s)),
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HDNVPTXISelLowering.cpp65 case MVT::v2i16: in IsPTXVectorType()
1909 case MVT::v2i16: in LowerSTOREVector()
4270 case MVT::v2i16: in ReplaceLoadVector()
/NextBSD/contrib/llvm/lib/IR/
HDValueTypes.cpp145 case MVT::v2i16: return "v2i16"; in getEVTString()
214 case MVT::v2i16: return VectorType::get(Type::getInt16Ty(Context), 2); in getTypeForEVT()
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenTarget.cpp87 case MVT::v2i16: return "MVT::v2i16"; in getEnumName()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZRegisterInfo.td233 defm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32,
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp172 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); in AMDGPUTargetLowering()
234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
HDSIISelLowering.cpp116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in SITargetLowering()
HDR600ISelLowering.cpp116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom); in X86TargetLowering()
972 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom); in X86TargetLowering()
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal); in X86TargetLowering()
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal); in X86TargetLowering()

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