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Searched refs:v4f32 (Results 1 – 25 of 60) sorted by relevance

123

/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrQPX.td78 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4f32;
83 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4f32;
88 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4f32;
121 [(set v4f32:$FRT, (fadd v4f32:$FRA, v4f32:$FRB))]>;
132 [(set v4f32:$FRT, (fsub v4f32:$FRA, v4f32:$FRB))]>;
142 [(set v4f32:$FRT, (PPCfre v4f32:$FRB))]>;
151 [(set v4f32:$FRT, (PPCfrsqrte v4f32:$FRB))]>;
164 [(set v4f32:$FRT, (fmul v4f32:$FRA, v4f32:$FRC))]>;
179 [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC, v4f32:$FRB))]>;
190 [(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC,
[all …]
HDPPCInstrAltivec.td316 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
459 [(set v4f32:$vD,
460 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
465 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
466 (fneg v4f32:$vB))))]>;
488 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
520 [(set v4f32:$vD,
524 [(set v4f32:$vD,
529 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
533 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
[all …]
HDPPCInstrVSX.td153 [(set v4f32:$XT, (fadd v4f32:$XA, v4f32:$XB))]>;
163 [(set v4f32:$XT, (fmul v4f32:$XA, v4f32:$XB))]>;
179 [(set v4f32:$XT, (fsub v4f32:$XA, v4f32:$XB))]>;
267 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
299 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
331 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
363 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
407 [(set v4f32:$XT, (fdiv v4f32:$XA, v4f32:$XB))]>;
416 [(set v4f32:$XT, (fsqrt v4f32:$XB))]>;
439 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>;
[all …]
HDPPCCallingConv.td60 CCIfType<[v4f64, v4f32, v4i1],
65 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
116 CCIfType<[v4f64, v4f32, v4i1],
118 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
162 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
176 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
180 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
HDPPCISelLowering.cpp504 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
505 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
506 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
507 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
509 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
514 setOperationAction(ISD::MUL, MVT::v4f32, Legal); in PPCTargetLowering()
515 setOperationAction(ISD::FMA, MVT::v4f32, Legal); in PPCTargetLowering()
518 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
531 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
[all …]
HDPPCRegisterInfo.td291 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32], 128,
298 def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
301 def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
307 def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
325 def QSRC : RegisterClass<"PPC", [v4f32], 128, (add QFRC)>;
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp59 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
105 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
106 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
115 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
116 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
117 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
118 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
119 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
129 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
[all …]
HDARMCallingConv.td28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
80 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
96 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
150 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
160 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
178 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
193 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
HDARMInstrNEON.td1105 def : Pat<(vector_insert (v4f32 QPR:$src),
1405 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
2092 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
3272 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3275 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
4112 v4f32, v4f32, fadd, 1>;
4167 v4f32, v4f32, fmul, 1>;
4170 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4185 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4186 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
196 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
208 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
209 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
210 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
211 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
224 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
227 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
239 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
240 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
[all …]
HDAArch64CallingConvention.td27 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
73 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
81 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
87 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
93 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
109 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
120 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
154 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
163 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
[all …]
HDAArch64ISelDAGToDAG.cpp2412 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2430 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2448 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2466 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2484 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2502 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2520 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2538 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2556 else if (VT == MVT::v4i32 || VT == MVT::v4f32) in Select()
2569 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
[all …]
HDAArch64InstrInfo.td1306 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1354 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1497 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1661 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1979 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
2008 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2074 def : Pat<(store (v4f32 FPR128:$Rt),
2169 def : Pat<(store (v4f32 FPR128:$Rt),
2278 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2332 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
[all …]
HDAArch64SchedA57.td415 // Q form - v4f32, v2f64
424 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
429 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
434 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f…
441 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i6…
461 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
465 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
472 def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
480 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
485 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp407 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
430 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, in getShuffleCost()
447 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd in getShuffleCost()
487 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, in getCastInstrCost()
488 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, in getCastInstrCost()
489 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, in getCastInstrCost()
490 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, in getCastInstrCost()
491 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, in getCastInstrCost()
492 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, in getCastInstrCost()
493 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, in getCastInstrCost()
[all …]
HDX86InstrFMA.td90 loadv8f32, X86Fmadd, v4f32, v8f32>;
92 loadv8f32, X86Fmsub, v4f32, v8f32>;
95 v4f32, v8f32>;
98 v4f32, v8f32>;
117 loadv8f32, X86Fnmadd, v4f32, v8f32>;
119 loadv8f32, X86Fnmsub, v4f32, v8f32>;
367 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
369 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
371 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
373 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
[all …]
HDX86InstrSSE.td333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
[all …]
HDX86CallingConv.td56 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
113 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
141 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
283 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
311 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
334 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
360 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
376 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
401 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
452 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
[all …]
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600Instructions.td384 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
479 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
485 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
491 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
496 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
499 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
510 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
515 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
520 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
525 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
[all …]
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineValueType.h99 v4f32 = 48, // 4 x f32 enumerator
229 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); in is128BitVector()
320 case v4f32: in getVectorElementType()
359 case v4f32: in getVectorNumElements()
435 case v4f32: in getSizeInBits()
580 if (NumElements == 4) return MVT::v4f32; in getVectorVT()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrVector.td126 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)),
143 def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)),
153 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
179 defm : ReplicatePeephole<VLREPF, v4f32, load, f32>;
201 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
230 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>;
238 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>;
252 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)),
337 defm : GenericVectorOps<v4f32, v4i32>;
848 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>;
[all …]
HDSystemZCallingConv.td54 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
84 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
91 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
96 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
/NextBSD/contrib/llvm/include/llvm/IR/
HDIntrinsicsNVVM.td1054 "llvm.nvvm.tex.1d.v4f32.s32">;
1058 "llvm.nvvm.tex.1d.v4f32.f32">;
1062 "llvm.nvvm.tex.1d.level.v4f32.f32">;
1067 "llvm.nvvm.tex.1d.grad.v4f32.f32">;
1106 "llvm.nvvm.tex.1d.array.v4f32.s32">;
1110 "llvm.nvvm.tex.1d.array.v4f32.f32">;
1115 "llvm.nvvm.tex.1d.array.level.v4f32.f32">;
1120 "llvm.nvvm.tex.1d.array.grad.v4f32.f32">;
1161 "llvm.nvvm.tex.2d.v4f32.s32">;
1165 "llvm.nvvm.tex.2d.v4f32.f32">;
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsMSAInstrInfo.td180 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
182 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
184 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
186 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
188 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
190 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
192 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
194 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
196 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
198 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/InstPrinter/
HDX86InstComments.cpp160 DecodeBLENDMask(MVT::v4f32, in EmitAnyX86InstComments()
263 DecodeMOVSLDUPMask(MVT::v4f32, ShuffleMask); in EmitAnyX86InstComments()
289 DecodeMOVSHDUPMask(MVT::v4f32, ShuffleMask); in EmitAnyX86InstComments()
651 DecodeSHUFPMask(MVT::v4f32, in EmitAnyX86InstComments()
701 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask); in EmitAnyX86InstComments()
753 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask); in EmitAnyX86InstComments()
778 DecodePSHUFMask(MVT::v4f32, in EmitAnyX86InstComments()
856 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask); in EmitAnyX86InstComments()

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