Home
last modified time | relevance | path

Searched refs:v4f64 (Results 1 – 23 of 23) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrQPX.td42 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
47 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
52 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB))]>;
57 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRC))]>;
62 [(set v4f64:$FRT, (IntID v4f64:$FRB))]>;
67 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB))]>;
72 [(set v4f64:$FRT, (IntID v4f64:$FRB))]>;
115 [(set v4f64:$FRT, (fadd v4f64:$FRA, v4f64:$FRB))]>;
126 [(set v4f64:$FRT, (fsub v4f64:$FRA, v4f64:$FRB))]>;
137 [(set v4f64:$FRT, (PPCfre v4f64:$FRB))]>;
[all …]
HDPPCISelLowering.cpp637 setOperationAction(ISD::FADD, MVT::v4f64, Legal); in PPCTargetLowering()
638 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); in PPCTargetLowering()
639 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); in PPCTargetLowering()
640 setOperationAction(ISD::FREM, MVT::v4f64, Expand); in PPCTargetLowering()
642 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal); in PPCTargetLowering()
643 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
645 setOperationAction(ISD::LOAD , MVT::v4f64, Custom); in PPCTargetLowering()
646 setOperationAction(ISD::STORE , MVT::v4f64, Custom); in PPCTargetLowering()
648 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
649 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
[all …]
HDPPCCallingConv.td60 CCIfType<[v4f64, v4f32, v4i1],
116 CCIfType<[v4f64, v4f32, v4i1],
159 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
176 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
HDPPCRegisterInfo.td323 def QFRC : RegisterClass<"PPC", [v4f64], 256, (add (sequence "QF%u", 0, 13),
HDPPCISelDAGToDAG.cpp2488 case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX in Select()
2757 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64) in Select()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrFMA.td103 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
105 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
108 v2f64, v4f64>, VEX_W;
111 v2f64, v4f64>, VEX_W;
123 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
126 v4f64>, VEX_W;
382 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
384 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
386 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
388 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
[all …]
HDX86TargetTransformInfo.cpp379 {ISD::VECTOR_SHUFFLE, MVT::v4f64, 1}, // vblendpd in getShuffleCost()
617 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost()
618 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, in getCastInstrCost()
619 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, in getCastInstrCost()
620 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, in getCastInstrCost()
630 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, in getCastInstrCost()
631 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, in getCastInstrCost()
632 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, in getCastInstrCost()
633 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, in getCastInstrCost()
640 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 4*10 }, in getCastInstrCost()
[all …]
HDX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
292 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
314 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
338 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
380 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
455 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
471 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
490 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
HDX86InstrSSE.td347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
[all …]
HDX86InstrAVX512.td423 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
HDX86InstrFragmentsSIMD.td472 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
485 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
554 (v4f64 (alignedload256 node:$ptr))>;
HDX86RegisterInfo.td448 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
473 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
HDX86ISelLowering.cpp1045 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); in X86TargetLowering()
1048 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); in X86TargetLowering()
1064 setOperationAction(ISD::FADD, MVT::v4f64, Legal); in X86TargetLowering()
1065 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); in X86TargetLowering()
1066 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); in X86TargetLowering()
1067 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); in X86TargetLowering()
1068 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in X86TargetLowering()
1069 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); in X86TargetLowering()
1070 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in X86TargetLowering()
1071 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal); in X86TargetLowering()
[all …]
HDX86InstrCompiler.td516 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineValueType.h104 v4f64 = 53, // 4 x f64 enumerator
234 return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
325 case v4f64: in getVectorElementType()
360 case v4f64: return 4; in getVectorNumElements()
442 case v4f64: return 256; in getSizeInBits()
587 if (NumElements == 4) return MVT::v4f64; in getVectorVT()
HDValueTypes.td77 def v4f64 : ValueType<256, 53>; // 4 x f64 vector value
/NextBSD/contrib/llvm/lib/Target/X86/InstPrinter/
HDX86InstComments.cpp146 DecodeBLENDMask(MVT::v4f64, in EmitAnyX86InstComments()
297 DecodeMOVDDUPMask(MVT::v4f64, ShuffleMask); in EmitAnyX86InstComments()
637 DecodeSHUFPMask(MVT::v4f64, in EmitAnyX86InstComments()
683 DecodeUNPCKLMask(MVT::v4f64, ShuffleMask); in EmitAnyX86InstComments()
735 DecodeUNPCKHMask(MVT::v4f64, ShuffleMask); in EmitAnyX86InstComments()
808 DecodePSHUFMask(MVT::v4f64, in EmitAnyX86InstComments()
/NextBSD/contrib/llvm/lib/IR/
HDValueTypes.cpp171 case MVT::v4f64: return "v4f64"; in getEVTString()
240 case MVT::v4f64: return VectorType::get(Type::getDoubleTy(Context), 4); in getTypeForEVT()
/NextBSD/contrib/llvm/include/llvm/IR/
HDIntrinsicsPowerPC.td750 /// PowerPC_QPX_FF_Intrinsic - A PowerPC intrinsic that takes one v4f64
756 /// PowerPC_QPX_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f64
763 /// PowerPC_QPX_FFFF_Intrinsic - A PowerPC intrinsic that takes three v4f64
772 /// and returns a v4f64.
778 /// and returns a v4f64 permutation.
784 /// and stores a v4f64.
HDIntrinsics.td201 def llvm_v4f64_ty : LLVMType<v4f64>; // 4 x double
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenTarget.cpp113 case MVT::v4f64: return "MVT::v4f64"; in getEnumName()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp213 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in NVPTXTargetLowering()
214 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); in NVPTXTargetLowering()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp266 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()