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Searched refs:AMDGPU_TILING_GET (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDdce_v10_0.c1872 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1951 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1954 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1955 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1956 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1957 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1958 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
1971 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
HDdce_v11_0.c1914 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
HDamdgpu_object.c1135 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
HDamdgpu_dm.c2082 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in fill_plane_attributes_from_fb()
2085 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_attributes_from_fb()
2086 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_plane_attributes_from_fb()
2087 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_plane_attributes_from_fb()
2088 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in fill_plane_attributes_from_fb()
2089 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in fill_plane_attributes_from_fb()
2101 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in fill_plane_attributes_from_fb()
2107 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in fill_plane_attributes_from_fb()
2127 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in fill_plane_attributes_from_fb()
/dragonfly/sys/dev/drm/include/uapi/drm/
HDamdgpu_drm.h333 #define AMDGPU_TILING_GET(value, field) \ macro