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Searched refs:AR_PCIE_PM_CTRL (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
HDar9300_power.c1099 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); in ar9300_wow_enable()
1110 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); in ar9300_wow_enable()
1112 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); in ar9300_wow_enable()
1346 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); in ar9300_wow_enable()
1352 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); in ar9300_wow_enable()
1510 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); in ar9300_wow_wake_up()
1514 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); in ar9300_wow_wake_up()
HDar9300_attach.c2384 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), in ar9300_attach()
2385 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | in ar9300_attach()
3150 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); in ar9300_config_pci_power_save()
4046 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = in ar9300_init_hostif_offsets()
4155 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = in ar9340_init_hostif_offsets()
HDar9300.h731 u_int32_t AR_PCIE_PM_CTRL; member
HDar9300_reset.c5324 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), in ar9300_reset()
/dragonfly/sys/dev/netif/ath/ath_hal/ar9002/
HDar9285_attach.c438 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9285ConfigPCIE()
479 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9285ConfigPCIE()
HDar9280_attach.c446 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9280ConfigPCIE()
483 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9280ConfigPCIE()
HDar9287_attach.c376 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9287ConfigPCIE()
/dragonfly/tools/tools/ath/common/
HDdumpregs_5416.c265 DEFBASIC(AR_PCIE_PM_CTRL, "PCIEPMC"),
/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
HDar5416_attach.c535 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar5416ConfigPCIE()
541 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar5416ConfigPCIE()
HDar5416reg.h35 #define AR_PCIE_PM_CTRL 0x4014 macro