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Searched refs:CSR_READ_1 (Results 1 – 25 of 37) sorted by relevance

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/dragonfly/sys/dev/netif/vge/
HDif_vgevar.h147 #define CSR_READ_1(sc, reg) \ macro
151 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
158 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
HDif_vge.c258 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) in vge_eeprom_getword()
298 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); in vge_read_eeprom()
311 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_stop()
329 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_start()
343 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) in vge_miipoll_start()
359 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) in vge_miibus_readreg()
373 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) in vge_miibus_readreg()
394 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) in vge_miibus_writereg()
411 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) in vge_miibus_writereg()
477 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) in vge_cam_set()
[all …]
/dragonfly/sys/dev/netif/re/
HDif_revar.h234 #define CSR_READ_1(sc, reg) \ macro
238 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
240 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))
HDre.c145 CSR_READ_1(sc, RE_EECMD) | x)
149 CSR_READ_1(sc, RE_EECMD) & ~x)
609 CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) | (BIT_6|BIT_7)); in re_phy_power_up()
744 CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) & ~BIT_6); in re_phy_power_down()
764 CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) & ~BIT_6); in re_phy_power_down()
765 CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~BIT_6); in re_phy_power_down()
770 CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) & ~(BIT_6|BIT_7)); in re_phy_power_down()
1150 CSR_WRITE_1(sc, RE_CFG5, CSR_READ_1(sc, RE_CFG5) & ~BIT_0); in DisableMcuBPs()
1151 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7); in DisableMcuBPs()
3534 CSR_WRITE_1(sc, RE_MCU_CMD, CSR_READ_1(sc, RE_MCU_CMD) & ~RE_NOW_IS_OOB); in re_disable_now_is_oob()
[all …]
/dragonfly/sys/dev/netif/vr/
HDif_vr.c210 CSR_READ_1(sc, reg) | (x))
214 CSR_READ_1(sc, reg) & ~(x))
234 CSR_READ_1(sc, VR_MIICMD) | (x))
238 CSR_READ_1(sc, VR_MIICMD) & ~(x))
368 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
376 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
430 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
440 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
527 rxfilt = CSR_READ_1(sc, VR_RXCFG); in vr_setmulti()
739 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); in vr_attach()
HDif_vrreg.h494 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/rl/
HDif_rl.c257 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
260 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
313 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) in rl_eeprom_getword()
352 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
355 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
561 rval = CSR_READ_1(sc, RL_MEDIASTAT); in rl_miibus_readreg()
698 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in rl_reset()
838 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); in rl_attach()
990 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { in rl_rxeof()
HDif_rlreg.h404 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/video/cxm/
HDcxm_i2c.c310 return CSR_READ_1(sc, CXM_REG_I2C_GETSCL); in cxm_iic_getscl()
323 return CSR_READ_1(sc, CXM_REG_I2C_GETSDA); in cxm_iic_getsda()
/dragonfly/sys/dev/netif/ste/
HDif_ste.c181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
714 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & in ste_txeoc()
792 IFNET_STAT_INC(ifp, collisions, CSR_READ_1(sc, STE_LATE_COLLS) in ste_stats_update()
793 + CSR_READ_1(sc, STE_MULTI_COLLS) in ste_stats_update()
794 + CSR_READ_1(sc, STE_SINGLE_COLLS)); in ste_stats_update()
HDif_stereg.h444 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/xl/
HDif_xl.c595 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); in xl_miibus_statchg()
731 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_setmulti()
767 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_setmulti_hash()
914 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); in xl_setmode()
2171 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { in xl_txeoc()
2404 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); in xl_stats_update_serialized()
2420 CSR_READ_1(sc, XL_W4_BADSSD); in xl_stats_update_serialized()
2784 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_init()
2872 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_init()
2987 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
[all …]
HDif_xlreg.h649 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/fxp/
HDif_fxp.c304 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) in fxp_scb_wait()
309 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), in fxp_scb_wait()
310 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), in fxp_scb_wait()
311 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), in fxp_scb_wait()
1207 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); in fxp_npoll_compat()
1266 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { in fxp_intr()
1525 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { in fxp_tick()
2238 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == in fxp_mc_setup()
HDif_fxpvar.h145 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/tx/
HDif_txvar.h116 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/msk/
HDif_msk.c976 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; in mskc_setup_rambuffer()
1439 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); in msk_attach()
1576 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); in mskc_attach()
1577 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; in mskc_attach()
1611 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); in mskc_attach()
1618 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == in mskc_attach()
1620 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) in mskc_attach()
2968 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); in msk_intr_gmac()
3382 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); in msk_init()
3630 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); in msk_set_rambuffer()
[all …]
/dragonfly/sys/dev/netif/stge/
HDif_stge.c219 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
221 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
307 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData; in stge_mii_readreg()
329 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData) in stge_mii_readreg()
406 error = CSR_READ_1(sc, STGE_PhyCtrl); in stge_miibus_readreg()
745 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & in stge_attach()
1871 v = CSR_READ_1(sc, STGE_PhySet); in stge_reset()
HDif_stgereg.h109 #define CSR_READ_1(_sc, reg) \ macro
/dragonfly/sys/dev/netif/wb/
HDif_wbreg.h397 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/my/
HDif_myreg.h391 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/lge/
HDif_lge.c644 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) in lge_list_rx_init()
954 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); in lge_txeof()
1145 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) { in lge_start()
HDif_lgereg.h559 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/tl/
HDif_tlreg.h502 #define CSR_READ_1(sc, reg) \ macro
/dragonfly/sys/dev/netif/wi/
HDif_wireg.h121 #define CSR_READ_1(sc, reg) \ macro

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