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Searched refs:CSR_READ_4 (Results 1 – 25 of 71) sorted by relevance

123

/dragonfly/sys/dev/netif/bfe/
HDif_bfe.c654 val = CSR_READ_4(sc, BFE_SBINTVEC); in bfe_pci_setup()
658 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); in bfe_pci_setup()
672 CSR_READ_4(sc, reg); in bfe_clear_stats()
674 CSR_READ_4(sc, reg); in bfe_clear_stats()
698 CSR_READ_4(sc, BFE_IMASK); in bfe_chip_halt()
717 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); in bfe_chip_reset()
725 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) in bfe_chip_reset()
744 val = CSR_READ_4(sc, BFE_DEVCTRL); in bfe_chip_reset()
747 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { in bfe_chip_reset()
792 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) in bfe_core_disable()
[all …]
/dragonfly/sys/dev/netif/mii_layer/
HDdcphy.c68 CSR_READ_4(sc, reg) | x)
72 CSR_READ_4(sc, reg) & ~x)
238 mode = CSR_READ_4(dc_sc, DC_NETCFG); in dcphy_service()
304 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_service()
350 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
354 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { in dcphy_status()
356 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
408 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) in dcphy_status()
412 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) in dcphy_status()
HDpnphy.c67 CSR_READ_4(sc, reg) | x)
71 CSR_READ_4(sc, reg) & ~x)
265 reg = CSR_READ_4(dc_sc, DC_ISR); in pnphy_status()
270 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) in pnphy_status()
274 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) in pnphy_status()
/dragonfly/sys/dev/netif/alc/
HDif_alc.c275 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
302 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
340 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
366 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
417 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_miibus_statchg()
461 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
492 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
674 opt = CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
675 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && in alc_get_macaddr_813x()
676 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { in alc_get_macaddr_813x()
[all …]
/dragonfly/sys/dev/netif/nge/
HDif_nge.c232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
235 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
249 CSR_READ_4(sc, NGE_CSR); in nge_delay()
332 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) in nge_eeprom_getword()
445 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; in nge_mii_readreg()
467 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) in nge_mii_readreg()
569 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); in nge_miibus_statchg()
637 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); in nge_setmulti()
[all …]
/dragonfly/sys/dev/netif/stge/
HDif_stge.c676 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) in stge_attach()
1089 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) in stge_dma_wait()
1330 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; in stge_link()
1336 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_link()
1341 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) in stge_link()
1356 txstat = CSR_READ_4(sc, STGE_TxStatus); in stge_tx_error()
1378 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | in stge_tx_error()
1789 CSR_READ_4(sc,STGE_OctetRcvOk); in stge_stats_update()
1791 IFNET_STAT_INC(ifp, ipackets, CSR_READ_4(sc, STGE_FramesRcvdOk)); in stge_stats_update()
1795 CSR_READ_4(sc, STGE_OctetXmtdOk); in stge_stats_update()
[all …]
/dragonfly/sys/dev/video/cxm/
HDcxm.c354 flags = CSR_READ_4(sc, in cxm_queue_firmware_command()
368 = CSR_READ_4(sc, in cxm_queue_firmware_command()
399 CSR_READ_4(sc, mailbox + offsetof(struct cxm_mailbox, flags)); in cxm_queue_firmware_command()
468 flags = CSR_READ_4(sc, in cxm_firmware_command()
483 result = CSR_READ_4(sc, in cxm_firmware_command()
489 = CSR_READ_4(sc, in cxm_firmware_command()
529 flags = CSR_READ_4(sc, in cxm_firmware_command_nosleep()
544 result = CSR_READ_4(sc, in cxm_firmware_command_nosleep()
550 = CSR_READ_4(sc, in cxm_firmware_command_nosleep()
595 CSR_READ_4(sc, CXM_REG_IRQ_MASK); in cxm_set_irq_mask()
[all …]
HDcxm_i2c.c292 CSR_READ_4(sc, CXM_REG_I2C_SETSDA); in cxm_iic_reset()
344 CSR_READ_4(sc, CXM_REG_I2C_SETSCL); in cxm_iic_setscl()
365 CSR_READ_4(sc, CXM_REG_I2C_SETSDA); in cxm_iic_setsda()
/dragonfly/sys/dev/netif/ale/
HDif_ale.c202 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_readreg()
238 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_writereg()
290 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_miibus_statchg()
357 reg = CSR_READ_4(sc, ALE_SPI_CTRL); in ale_get_macaddr()
369 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
373 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); in ale_get_macaddr()
386 ea[0] = CSR_READ_4(sc, ALE_PAR0); in ale_get_macaddr()
387 ea[1] = CSR_READ_4(sc, ALE_PAR1); in ale_get_macaddr()
518 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { in ale_attach()
547 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> in ale_attach()
[all …]
/dragonfly/sys/dev/netif/age/
HDif_age.c197 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_readreg()
229 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_writereg()
280 reg = CSR_READ_4(sc, AGE_MAC_CFG); in age_miibus_statchg()
282 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | in age_miibus_statchg()
377 reg = CSR_READ_4(sc, AGE_SPI_CTRL); in age_get_macaddr()
468 ea[0] = CSR_READ_4(sc, AGE_PAR0); in age_get_macaddr()
469 ea[1] = CSR_READ_4(sc, AGE_PAR1); in age_get_macaddr()
576 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> in age_attach()
598 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), in age_attach()
599 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); in age_attach()
[all …]
/dragonfly/sys/dev/netif/jme/
HDif_jme.c301 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_readreg()
337 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_writereg()
564 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_eeprom_read_byte()
579 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
589 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
645 par0 = CSR_READ_4(sc, JME_PAR0); in jme_reg_macaddr()
646 par1 = CSR_READ_4(sc, JME_PAR1); in jme_reg_macaddr()
823 reg = CSR_READ_4(sc, JME_CHIPMODE); in jme_attach()
889 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_attach()
906 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & in jme_attach()
[all …]
/dragonfly/sys/dev/netif/sis/
HDif_sis.c205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
208 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
237 CSR_READ_4(sc, SIS_CSR); in sis_delay()
320 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) in sis_eeprom_getword()
420 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_read_mac()
421 csrsave = CSR_READ_4(sc, SIS_CSR); in sis_read_mac()
523 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; in sis_mii_readreg()
545 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) in sis_mii_readreg()
[all …]
/dragonfly/sys/dev/netif/lge/
HDif_lge.c199 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
202 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x))
208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x))
223 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0) in lge_eeprom_getword()
232 val = CSR_READ_4(sc, LGE_EEDATA); in lge_eeprom_getword()
273 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) in lge_miibus_readreg()
282 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); in lge_miibus_readreg()
295 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) in lge_miibus_writereg()
387 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0) in lge_reset()
[all …]
/dragonfly/sys/dev/netif/bge/
HDif_bge.c541 CSR_READ_4(sc, off); in bge_writembx()
553 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) in bge_nvram_getbyte()
561 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); in bge_nvram_getbyte()
568 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { in bge_nvram_getbyte()
580 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); in bge_nvram_getbyte()
589 CSR_READ_4(sc, BGE_NVRAM_SWARB); in bge_nvram_getbyte()
645 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) in bge_eeprom_getbyte()
655 byte = CSR_READ_4(sc, BGE_EE_DATA); in bge_eeprom_getbyte()
708 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
711 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
[all …]
HDif_bgevar.h77 #define CSR_READ_4(sc, reg) \ macro
81 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
84 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
102 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
/dragonfly/sys/dev/misc/ecc/
HDecc_e3.c161 CSR_READ_4(struct ecc_e3_softc *sc, int ofs) in CSR_READ_4() function
216 CSR_READ_4(sc, MCH_E3_ERRLOG0_C0)); in ecc_e3_attach()
218 CSR_READ_4(sc, MCH_E3_ERRLOG0_C1)); in ecc_e3_attach()
221 dimm_ch0 = CSR_READ_4(sc, MCH_CORE_DIMM_CH0); in ecc_e3_attach()
222 dimm_ch1 = CSR_READ_4(sc, MCH_CORE_DIMM_CH1); in ecc_e3_attach()
431 err0 = CSR_READ_4(sc, chan->chan_errlog0); in ecc_e3_errlog_ch()
/dragonfly/sys/dev/misc/coremctl/
HDcoremctl.c71 #define CSR_READ_4(sc, ofs) \ macro
263 dimm_ch0 = CSR_READ_4(sc, MCH_CORE_DIMM_CH0); in coremctl_attach()
264 dimm_ch1 = CSR_READ_4(sc, MCH_CORE_DIMM_CH1); in coremctl_attach()
281 ptm_ctl = CSR_READ_4(sc, MCH_CORE_DDR_PTM_CTL0); in coremctl_attach()
369 *val = CSR_READ_4(sc, reg); in coremctl_mch_readreg()
/dragonfly/sys/dev/netif/dc/
HDif_dc.c328 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
331 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
342 CSR_READ_4(sc, DC_BUSCTL); in dc_delay()
378 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { in dc_eeprom_width()
494 r = CSR_READ_4(sc, DC_SIO); in dc_eeprom_getword_pnic()
516 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; in dc_eeprom_getword_xircom()
519 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; in dc_eeprom_getword_xircom()
557 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) in dc_eeprom_getword()
627 CSR_READ_4(sc, DC_SIO); in dc_mii_readbit()
630 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) in dc_mii_readbit()
[all …]
/dragonfly/sys/dev/netif/wb/
HDif_wb.c214 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
217 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
220 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x))
223 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x))
276 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) in wb_eeprom_getword()
390 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; in wb_mii_readreg()
416 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) in wb_mii_readreg()
538 rxfilt = CSR_READ_4(sc, WB_NETCFG); in wb_setmulti()
585 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) { in wb_setcfg()
591 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && in wb_setcfg()
[all …]
/dragonfly/sys/dev/netif/vge/
HDif_vgevar.h143 #define CSR_READ_4(sc, reg) \ macro
155 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
162 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
/dragonfly/sys/dev/netif/bnx/
HDif_bnx.c440 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) in bnx_eeprom_getbyte()
450 byte = CSR_READ_4(sc, BGE_EE_DATA); in bnx_eeprom_getbyte()
503 val = CSR_READ_4(sc, BGE_MI_COMM); in bnx_miibus_readreg()
506 val = CSR_READ_4(sc, BGE_MI_COMM); in bnx_miibus_readreg()
554 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { in bnx_miibus_writereg()
556 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ in bnx_miibus_writereg()
617 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & in bnx_miibus_statchg()
1121 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); in bnx_chipinit()
1128 val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5); in bnx_chipinit()
1136 val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); in bnx_chipinit()
[all …]
HDif_bnxvar.h77 #define CSR_READ_4(sc, reg) \ macro
81 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
84 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
102 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
/dragonfly/sys/dev/netif/ti/
HDif_ti.c263 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; in ti_eeprom_putbyte()
288 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
297 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
305 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
316 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
327 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) in ti_eeprom_getbyte()
1033 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); in ti_setmulti()
1068 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) { in ti_64bitslot_war()
1072 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { in ti_64bitslot_war()
1112 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { in ti_chipinit()
[all …]
/dragonfly/sys/dev/powermng/memtemp/
HDmemtemp_core.c119 CSR_READ_4(struct memtemp_core_softc *sc, int ofs) in CSR_READ_4() function
191 dimm_ch = CSR_READ_4(sc, dimm_ch_reg); in memtemp_core_chan_attach()
266 val = CSR_READ_4(dimm_sc->dimm_parent, dimm_sc->dimm_reg); in memtemp_core_sensor_task()
/dragonfly/sys/dev/netif/tx/
HDif_tx.c666 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) { in epic_intr()
678 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0) in epic_intr()
1031 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) { in epic_miibus_mediainit()
1107 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT)); in epic_init()
1239 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE); in epic_stop_activity()
1249 status = CSR_READ_4(sc, INTSTAT); in epic_stop_activity()
1320 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) in epic_queue_last_packet()
1325 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0) in epic_queue_last_packet()
1551 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break; in epic_read_phy_reg()
1555 return (CSR_READ_4(sc, MIIDATA)); in epic_read_phy_reg()
[all …]

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