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Searched refs:DCLK (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/inc/
HDpower_state.h137 uint32_t DCLK; member
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDprocesspptables.c761 ps->uvd_clocks.DCLK = pnon_clock_info->ulDCLK; in init_non_clock_fields()
764 ps->uvd_clocks.DCLK = 0; in init_non_clock_fields()
HDsmu10_hwmgr.c760 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu10_dpm_get_pp_table_entry()
HDsmu7_hwmgr.c3164 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3257 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v1()
3405 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v0()
HDsmu8_hwmgr.c1383 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
HDvega10_hwmgr.c3021 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()
3088 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()
/dragonfly/sys/dev/drm/i915/
HDi915_reg.h3400 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) macro
HDintel_pm.c6869 min_ring_freq = I915_READ(DCLK) & 0xf; in gen6_update_ring_freq()