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Searched refs:DPLLB_LVDS_P2_CLOCK_DIV_7 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDintel_display.c6871 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
8226 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ironlake_compute_dpll()
10081 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
HDi915_reg.h3092 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ macro